Synthesizable flip-flop based phase-frequency comparator for phase-locked loops

Abstract

A method of performing phase-frequency comparison comprising the steps of receiving first and second clock signals; comparing the signals by triggering flip-flop circuits controlled by AND gates, and providing a first output when first signal is in advance of the second signal, and a second output when second signal is advance of the first signal.

I claim: 
     
       1. A method of performing phase-frequency comparison comprising the steps of: (a) receiving first and second clock signals,   (b) inputting said first and second clock signals to first and second logic AND gates,   (c) comparing said signals by triggering two negative-edge triggered flip-flops and two positive-edge triggered flip-flops controlled by said first and second logic AND gates, and   (d) providing a first output when said first clock signal is in advance of said second clock signal, and a second output when said second clock signal is in advance of said first clock signal.   
     
     
       2. A synthesizable, flip-flop based comparator for detecting a phase-frequency relationship between two clock signals, comprising: a) first and second AND gates with input terminals receiving first and second clock signals to be compared,   b) first and second negative-edge triggered flip-flops receiving said first and second clock signals; and   c) first and second positive-edge triggered flip-flops receiving said first and second clock signals, one of said positive-edge triggered flip-flops providing an output when said first clock signal is ahead of said second clock signal, the other positive-edge triggered flip-flop providing an output when said second clock signal is ahead of said first clock signal.   
     
     
       3. A synthesizable flip-flop based phase-frequency comparator for providing outputs when first and second clock signals are not in synchronism comprising: a first input terminal for receiving a first clock signal,   a second input terminal for receiving a second clock signal,   a first AND gate having an input connected to said first input terminal,   a second AND gate having an input connected to said second input terminal,   a first positive edge triggered D flip-flop having its clock input connected to said first input terminal,   a second positive edge triggered D flip-flop having its clock input connected to said second input terminal,   the Q output of said first positive-edge triggered D flip-flop being connected to a first output terminal for providing an UP signal indicating that said first clock signal is in advance of the said second clock signal,   said Q output also being connected to a first inverter,   said first inverter output being connected to the data input of said second positive-edge triggered D flip-flop,   a third negative edge triggered flip-flop having its clock terminal connected to the Q output of said first flip-flop,   the Q output of said third negative-edge triggered flip-flop being connected to a second inverter and said second inverter output being connected to an input of said second AND gate,   the output of said second AND gate being connected to the reset terminal of said first positive-edge triggered flip-flop,   the Q output of said second positive-edge triggered flip-flop being connected to a second output terminal for providing a DOWN signal indicating that said second clock signal is in advance of said first clock signal,   the Q output of said second positive-edge triggered flip-flop also being connected to a third inverter,   the output of said third inverter being connected to the data input of said first positive-edge triggered flip-flop,   the Q output of said second positive-edge triggered flip-flop also being connected to the clock input of a fourth negative edge triggered flip-flop,   the Q output of said fourth negative-edge triggered flip-flop being connected to the input of a fourth inverter,   the output of the fourth inverter being connected to an input of said first AND gate,   the output of said first AND gate being connected to the reset terminal of said second positive-edge triggered flip-flop,   the second input terminal being connected to the clock terminal of said second positive-edge triggered flip-flop and to the reset terminal of said third negative-edge triggered flip-flop,   the first input terminal being connected to the reset terminal of said fourth negative-edge triggered flip-flop,   whereby said UP signal is preset at said first output terminal when said first clock signal is ahead of said second clock signal, and said DOWN signal is present at said second output terminal when said second clock signal is ahead of said first clock signal.