Digital clock frequency multiplication circuit and method

Abstract

A clock frequency multiplier with a rise detector flip-flop connected to a series of buffers having interspersed parallel output taps connected to a binary to Gray converter for providing real time rise status indications. The parallel tap outputs are connected to first, second and third multiplexers, to produce first and second fall outputs and a second rise output. The multiplexers are controlled by first, second and third corresponding tap circuits having hexadecimal inputs from a Gray to hexadecimal converter connected to the output of the binary to Gray converter through a flip-flop clocked by a second rise of the input clock signal.

What is claimed is: 
     
       1. A frequency multiplier circuit comprising: a first signal detector for detecting a predetermined portion of a clock signal;   a plurality of delay elements for receiving clock signals, said plurality of delay elements connected in series at respective taps, and including first through nth respective delay elements and corresponding first through nth respective taps, the output of a particular delay element being connected to a corresponding one of said taps, said first clock signal detector being connected to said first delay element and being effective for providing information as to the initiation of an input clock signal;   a code device connected to said respective first through nth taps, to provide information on the passage of a signal through said plurality of delay elements; and   a multiplexer circuit having an output connection and a plurality of input connections respectively connected to said first through nth taps, said output connection producing output signals having information defined features and corresponding to input signals received by said first signal detector including first, second, and third multiplexers, each having an output connection and a plurality of input connections respectively connected to said first through nth taps, for producing information of selected signal features of output signals corresponding to input signals received by said first signal detector.   
     
     
       2. A frequency multiplier circuit comprising: a first signal detector for detecting a predetermined portion of a clock signal;   a plurality of delay elements for receiving clock signals, said plurality of delay elements connected in series at respective taps, and including first through nth respective delay elements and corresponding first through nth respective taps, the output of a particular delay element being connected to a corresponding one of said taps, said first clock signal detector being connected to said first delay element and being effective for providing information as to the initiation of an input clock signal;   a code device connected to said respective first through nth taps, to provide information on the passage of a signal through said plurality of delay elements; and   a multiplexer circuit having an output connection and a plurality of input connections respectively connected to said first through nth taps, said output connection producing output signals having information defined features and corresponding to input signals received by said first signal detector including first, second, and third multiplexers, each having an output connection and a plurality of input connections respectively connected to said first through nth taps, for producing information of selected signal features of output signals corresponding to input signals received by said first signal detector including first, second, and third tap set circuits connected respectively to said first, second, and third multiplexers, for producing information of successive signal features corresponding to said input signals.   
     
     
       3. A frequency multiplier circuit comprising: a first signal detector for detecting a predetermined portion of a clock signal;   a plurality of delay elements for receiving clock signals, said plurality of delay elements connected in series at respective taps, and including first through nth respective delay elements and corresponding first through nth respective taps, the output of a particular delay element being connected to a corresponding one of said taps, said first clock signal detector being connected to said first delay element and being effective for providing information as to the initiation of an input clock signal;   a code device connected to said respective first through nth taps, to provide information on the passage of a signal through said plurality of delay elements; and   a multiplexer circuit having an output connection and a plurality of input connections respectively connected to said first through nth taps, said output connection producing output signals having information defined features and corresponding to input signals received by said first signal detector including first, second, and third multiplexers, each having an output connection and a plurality of input connections respectively connected to said first through nth taps, for producing information of selected signal features of output signals corresponding to input signals received by said first signal detector including first, second, and third tap set circuits connected respectively to said first, second, and third multiplexers, for producing information of successive signal features corresponding to said input signals, wherein said successive signal features are the second fall, the second rise, and the first fall of output signals to be constructed.   
     
     
       4. A frequency multiplier circuit according to claim 2 wherein said first, second, and third tap set circuits further provide respective 25, 50, and 75 percent tap settings for control of respective ones of said first, second, and third multiplexers. 
     
     
       5. A clock frequency modifier method including: producing a coded representation of the progress of a selected feature of a clock pulse having four features of a first frequency waveform on a multiple element delay;   applying a selected integer to said coded representation to produce a counterpart to the third feature of said four feature first frequency waveform, at a second selected frequency waveform having corresponding four features;   applying half said selected integer to said coded representation to produce a counterpart to the second feature of said four feature first frequency waveform at said second selected frequency; and   applying one and a half of said selected integer to said coded representation to produce a counterpart to the fourth feature of said four feature first frequency waveform at said second selected frequency.   
     
     
       6. A frequency multiplier circuit comprising: a signal detector for detecting a selected clock pulse edge of a clock signal, said signal detector providing as output a detected signal;   a plurality of delay elements each having an input and an output, the plurality of delay elements connected in series such that there is a first delay element and a last delay element in the series, the output of the signal detector being connected to the input of the first delay element, the plurality of delay elements delaying the detected signal;   a monitor circuit connected to said outputs of the plurality of delay elements, said monitor circuit monitoring progress of the selected clock pulse edge during a clock period in the plurality of delay elements, the monitoring circuit providing as output information on the progress of the selected clock pulse edge in the plurality of delay elements; and   a multiplexer circuit receiving as input the outputs of the plurality of delay elements, the multiplexer circuit receiving as a control signal the output of the monitor circuit, in response to information of the progress of the selected clock pulse edge in the plurality of delay elements in a clock period from the monitor circuit, the multiplexer circuit producing output signals indicating clock pulse edges that when combined with the output of the signal detector producing a multiplication of the clock signal.   
     
     
       7. The frequency multiplier circuit of claim 6, wherein the monitor circuit monitoring the progress of the selected clock pulse edge during a clock period in the plurality of delay elements by counting the number of times the selected clock edge is produced by the plurality of delay elements in the clock period. 
     
     
       8. The frequency multiplier circuit of to claim 7, wherein the multiplexer circuit comprising: a first tap set circuit receiving as input the output of the monitor circuit, the first tap set circuit is being set at a first tap setting to produce a first control signal in response to the output of the monitor circuit;   a first multiplexer receiving as input the outputs of the plurality of delay; elements, the first multiplexer further receiving as input the first control signal, in response to the first control signal, the first multiplexer selectively allowing one of the outputs of the plurality of delay elements to pass through as an output signal;   a second tap set circuit receiving as input the output of the monitor circuit, the second tap set circuit is being set at a second tap setting to produce a second control signal in response to the output of the monitor circuit;   a second multiplexer receiving as input the outputs of the plurality of delay; elements, the second multiplexer further receiving as input the second control signal, in response to the second control signal, the second multiplexer selectively allowing one of the outputs of the plurality of delay elements to pass through as an output signal;   a third tap set circuit receiving as input the output of the monitor circuit, the third tap set circuit is being set at a third tap setting to produce a third control signal in response to the output of the monitor circuit; and   a third multiplexer receiving as input the outputs of the plurality of delay; elements, the third multiplexer further receiving as input the third control signal, in response to the third control signal, the third multiplexer selectively allowing one of the outputs of the plurality of delay elements to pass through as an output signal.   
     
     
       9. The frequency multiplier circuit of claim 8, wherein the signal detector detecting a first clock pulse rise edge and providing as output a signal carrying information on the first clock pulse rise edge, the output signal from the first multiplexer carrying information on a first clock pulse fall edge, the output signal from the second multiplexer carrying information on a second clock pulse rise edge, and the output signal from the third multiplexer carrying information on a second clock pulse fall edge, wherein the output signals from the signal detector and the first, second, and third multiplexers combined to produce a multiplication of the clock signal. 
     
     
       10. The frequency multiplier circuit of claim 7, wherein the monitor circuit comprising: a binary-to-Gray converter receiving as input the outputs of plurality of delay elements, the binary-to-Gray converter counting the number of the selected clock edges produced by the plurality of delay elements in the clock period, the binary-to-gray converter outputting a Gray-code based count signal;   a latch circuit receiving as input the Gray-code based count signal from the binary-to-Gray converter, the latch circuit providing a latched Gray-code based count signal as an output; and   a Gray-to-hex converter receiving as input the latched Gray-code based count signal from the latch circuit, the Gray-to-hex converter converting the latched Gray-code based count signal into a hexadecimal based count signal, the Gray-to-hex converter providing the hexadecimal based count signal as the output of the monitor circuit.   
     
     
       11. A method for multiplying a signal in reference to another signal comprising: detecting a selected clock pulse edge of a clock signal;   supplying a signal related to the selected clock pulse edge;   sequentially delaying the signal using a plurality of delay elements;   monitoring progress of the selected clock pulse edge during a clock period in the plurality of delay elements;   producing signals indicating other clock pulse edges in response to the monitored progress of the selected clock pulse edge in the plurality of delay elements in a clock period; and   combining information from the signal related to the selected clock pulse edge with information from the signals indicating other clock pulse edges to form a multiplication of the clock signal.   
     
     
       12. The method of claim 11 wherein the monitoring step involves counting the number of times the selected clock edge is produced by the plurality of delay elements in the clock period. 
     
     
       13. The method of claim 12, wherein the detecting step involves detecting a first clock pulse rise edge. 
     
     
       14. The method of claim 13, wherein the producing step involves producing signals carrying information on a first clock pulse fall edge, information on a second clock pulse rise edge, and information on a second clock pulse fall edge.