Page buffer for a multi-level flash memory with a limited number of latches per memory cell

Abstract

A page buffer for a multi-level flash memory array as at least two less latches than threshold values which may be programmed into a memory cell. To enable use of such a page buffer a program/verify method for each cell programs a cell to the level of a most significant binary bit indicating the programming state for the cell. For example, when three threshold levels vt1, vt2 and vt3 are used, the most significant bit representing the threshold level to be programmed is stored in a page buffer latch (312) and the next most significant bit is stored in a page buffer latch (311). The latch (312) is read first and the cell (300) is programmed to vt2 if latch (312) stores a 0. During the program verify procedure, once the vt2 level is obtained, the latch (312) will toggle to a 1. To reuse the latch (312), the latch (312) is then preset to 0, and a read is performed with the latch (312) enabled if latch (311) stores a 0, enabling latch (312) to transition to a 1 if the memory cell (300) is to be programmed to a level vt3. A read is also performed with latch (311) enabled to enable latch (311) to transition to a 1 if the cell (300) is already programmed to vt2. If the latch (312) now stores a 1, the cell (300) is programmed to the level vt3. If the latch (311) stores a 0, the cell (300) is programmed to the level vt1. By reusing the latch (312) to represent the vt3 level in this manner, the third latch (313) is no longer required for programming.

What is claimed is: 
     
       1. An integrated circuit comprising: an array of flash memory cells, each cell having a control gate connected to a wordline in a row of wordlines, and a drain connected to a bitline in a column of bitlines;   a power supply receiving a control signal, the power supply being coupled to the bitlines and the wordlines for providing power supply signals;   a processor providing control signals to the power supply to enable selective reading of one of N possible threshold states stored by one of the flash memory cells, wherein N is an integer; and   a page buffer comprising groups of latches each coupled to a given one of the bitlines, wherein each group of latches includes a number of latches limited to at least two less than the N possible threshold states per memory cell connected to the given bitline.   
     
     
       2. The integrated circuit of claim 1 wherein each group of latches further comprises: a current source connected to a first node;   latch enable transistors, each having a source to drain path coupling one of the latches in the group of latches to a first node;   a current sink transistor having a gate coupled to the given bitline and a source to drain path connecting the first node to a first voltage potential; and   a current source connected to the first node, the current source sourcing less current than the current sink.   
     
     
       3. The integrated circuit of claim 1, wherein the control signals provided by the processor cause the power supply to provide N voltage levels to the wordlines to enable reading of the N possible threshold states.