Semiconductor structure having a titanium barrier layer

Abstract

A semiconductor structure (10)includes a semiconductor substrate (12), a silicon layer (18)overlying the semiconductor substrate, a dielectric layer (16)overlying the silicon layer and having a contact opening to expose a portion of the silicon layer, and a metal layer stack (20)overlying the dielectric layer and having a portion in contact with the silicon layer through the contact opening. The metal layer stack comprises a barrier layer (24)of titanium with incorporated oxygen (of greater than about 11 atomic percent) to provide diffusion resistance against, for example, platinum, oxygen, and silicon.

I claim: 
     
       1. A method for manufacturing a semiconductor structure comprising the steps of: providing a semiconductor substrate; and   forming a barrier layer overlying said semiconductor substrate wherein said barrier layer comprises titanium and oxygen atoms and is formed to have an atomic concentration of said oxygen of greater than about 11%, and wherein the barrier layer is deposited and the oxygen atoms are incorporated into the titanium crystal structure during the deposition of the barrier layer and at a temperature legs than approximately 450° C.   
     
     
       2. A method for manufacturing a semiconductor structure comprising the steps of: providing a semiconductor substrate; and   forming a barrier layer overlying said semiconductor substrate wherein said barrier layer consists essentially of titanium and oxygen atoms, and wherein the barrier layer is deposited and the oxygen atoms are incorporated into the titanium crystal structure during the deposition of the barrier layer and at a temperature less than approximately 450° C.   
     
     
       3. The method for manufacturing said semiconductor structure of claim 2 wherein said step of forming said barrier layer provides said barrier layer with an atomic concentration of said oxygen of greater than about 11%. 
     
     
       4. The method for manufacturing said semiconductor structure of claim 2 wherein said step of forming said barrier layer provides said barrier layer with an atomic concentration of said oxygen of about 11-30%. 
     
     
       5. The method for manufacturing said semiconductor structure of claim 2 further comprising the step of forming a dielectric layer overlying said semiconductor substrate prior to said step of forming said barrier layer. 
     
     
       6. The method for manufacturing said semiconductor structure of claim 2 further comprising the step of forming a top metal layer overlying said barrier layer and wherein said step of forming said barrier layer comprises the step of incorporating said oxygen into said barrier layer to a concentration sufficient to substantially block diffusion from said top metal layer through said barrier layer. 
     
     
       7. The method for manufacturing said semiconductor structure of claim 6 further comprising the step of patterning said top metal layer and said barrier layer using lift-off processing. 
     
     
       8. The method for manufacturing said semiconductor structure of claim 6 wherein said top metal layer comprises platinum. 
     
     
       9. The method for manufacturing said semiconductor structure of claim 6 further comprising the step of forming an adhesion layer overlying a dielectric layer and underlying said barrier layer. 
     
     
       10. The method for manufacturing said semiconductor structure of claim 9 wherein said adhesion layer comprises chromium. 
     
     
       11. The method for manufacturing said semiconductor structure of claim 2 wherein said step of forming said barrier layer comprises incorporating said oxygen into said barrier layer from a supply gas containing oxygen atoms. 
     
     
       12. The method for manufacturing said semiconductor structure of claim 11 wherein said supply gas comprises at least one member of the group consisting of diatomic oxygen and water. 
     
     
       13. The method for manufacturing said semiconductor structure of claim 11 wherein said step of forming said barrier layer is performed at a pressure of greater than about 2×10 -6  Pa. 
     
     
       14. The method for manufacturing said semiconductor structure of claim 11 wherein said step of forming said barrier layer is performed at a deposition rate of less than about 10 angstroms/second.