Method and apparatus for manufacturing pre-terminated chips

Abstract

A method and apparatus for forming edge terminations in multi-layer electrical component chips, such as capacitor chips, is arranged to cut holes through a laminated printed circuit pad at locations corresponding to the boundaries between adjacent chips when the pad is subsequently cut into individual chips. The holes are then filled with conductive ink to form plugs spanning the boundaries. The pad is then cut along a grid of perpendicular cutting lines defining the individual chip areas, simultaneously cutting through each of the ink plugs so that the cut ink plugs form the appropriate edge terminations along each side edge of a chip. The cutting device is suitably programmed to cut holes over the areas corresponding to the desired edge termination sizes and positions.

We claim: 
     
       1. A method of forming multi-layer electrical component chips with built-in edge terminations, comprising the steps of: taking a laminated pad of individual printed circuit wafers for cutting into individual rectangular chips;   cutting holes through the pad at predetermined spaced positions on the pad, the holes defining a first set of parallel linear paths across the pad and a second set of parallel linear paths extending perpendicular to the second set to form a rectangular grid;   filling each of the cut holes with conductive ink to form a conductive ink plug;   drying the ink plugs; and   cutting the pad through each of the perpendicular sets of linear paths defined by the ink plugs to form a plurality of individual chips, with each ink plug being cut in half to form a first edge termination along one side edge of one chip and a second edge termination along an adjacent side edge of another chip.   
     
     
       2. The method as claimed in claim 1, wherein the step of cutting holes along the first and second sets of parallel linear paths includes lining up a cutting device on each of the linear paths using fiducial markings at the edges of the pad. 
     
     
       3. The method as claimed in claim 1, including the step of marking an upper surface of the pad with a grid of intersecting lines corresponding to said first and second sets of linear paths dividing the pad into individual rectangular chip areas, prior to cutting holes through the pad at predetermined positions along each of the lines. 
     
     
       4. The method as claimed in claim 1, wherein the pad has electrodes of conductive ink and the conductive ink filling the cut holes is the same ink as the pad electrode ink. 
     
     
       5. The method as claimed in claim 4, including the step of placing the cut chips into a firing kiln and firing the chips so as to fire the electrode ink and the edge termination ink simultaneously. 
     
     
       6. The method as claimed in claim 1, wherein at least one hole is cut along each edge of each of the rectangular chip areas. 
     
     
       7. The method as claimed in claim 1, wherein the holes include circular holes and elongated holes. 
     
     
       8. The method as claimed in claim 1, wherein the holes are laser cut. 
     
     
       9. An apparatus for forming edge terminations in multi-layer electrical component chips, comprising: a punching device for punching holes through the pad at predetermined spaced locations along a first set of parallel linear paths across the pad and a second set of parallel linear paths extending perpendicular to the first set to form a rectangular grid;   a controller for controlling the punching device to punch the holes at said predetermined positions corresponding to predetermined edge terminations at each chip edge;   a hole filling device for filling the cut holes with conductive ink to form a conductive ink plug;   a drying oven for drying the conductive ink plugs;   a cutting device for cutting the pad along each of the intersecting linear paths and through each ink plug along each of the lines to form a plurality of individual chips, with each ink plug being cut in half to form a first edge termination along one side edge of one chip and a second edge termination along an adjacent side edge of another chip.