Lateral SRAM transistor circuits and methods of fabrication therefor

Abstract

A substrate transistor is formed, including a gate insulation region formed on a substrate, spaced apart source/drain regions formed in the substrate, and a gate electrode formed on the gate insulation region, disposed between the spaced apart source/drain regions, the gate electrode having a sidewall portion. A lateral thin film transistor is formed, including a sidewall gate insulation region on the sidewall portion of the gate electrode and a lateral channel region on the sidewall gate insulation region such that the gate electrode controls the current in the lateral channel region. A first one of the spaced apart source/drain regions of the substrate transistor preferably includes a lightly-doped inner portion disposed adjacent the gate electrode and a heavily-doped outer portion disposed adjacent the lightly-outer portion, opposite the gate electrode. The lateral channel region preferably is electrically connected to a second one of the spaced-apart source/drain regions of the substrate transistor. The sidewall gate insulation region contacts the lateral channel region at a first surface of the lateral channel region, and an auxiliary gate may be formed on a second surface of the lateral channel region, the auxiliary gate including an auxiliary gate insulation region on the lateral channel region and an auxiliary gate electrode on the auxiliary gate insulation region. The auxiliary gate electrode preferably is formed on an insulation region formed on the substrate, extends from the insulation region to overlie portions of the lateral channel region.

That which is claimed is: 
     
       1. A static random access memory (SRAM) cell, comprising: a substrate transistor including a gate insulation region on a substrate, spaced apart source/drain regions in said substrate, and a gate electrode on said gate insulation region, disposed between said spaced apart source/drain regions, said gate electrode having a top face, a bottom face and a sidewall portion extending therebetween; and   a lateral thin film load transistor including a sidewall gate insulation region on said sidewall portion of said gate electrode between said top face and said bottom face and a lateral channel region on said sidewall gate insulation region between said top face and said bottom face such that said gate electrode controls the current in said lateral channel region between said top face and said bottom face, along a direction parallel to said substrate.   
     
     
       2. An SRAM according to claim 1 wherein said substrate has first conductivity type, wherein said spaced apart source/drain regions have second conductivity type, and wherein said lateral channel region has first conductivity type. 
     
     
       3. An SRAM according to claim 2 wherein said spaced apart source/drain regions comprise n-doped silicon, and wherein said lateral channel region comprises at least one of polycrystalline silicon and amorphous silicon. 
     
     
       4. An SRAM cell according to claim 1: wherein a first one of the spaced apart source/drain regions of said substrate transistor comprises: a lightly-doped inner portion disposed adjacent said gate electrode; and   a heavily-doped outer portion disposed adjacent the lightly-outer portion, opposite said gate electrode; and     wherein a second of the spaced apart source/drain regions comprises a lightly-doped source/drain region having an impurity concentration lower than said heavily-doped outer portion of said first source/drain region.   
     
     
       5. An SRAM cell according to claim 1 wherein said lateral channel region is electrically connected to one of said spaced-apart source/drain regions of said substrate transistor. 
     
     
       6. A static random access memory (SRAM) cell, comprising: a substrate transistor including a gate insulation region on a substrate, spaced apart source/drain regions in said substrate, and a gate electrode on said gate insulation region, disposed between said spaced apart source/drain regions, said gate electrode having a top face, a bottom face and a sidewall portion extending therebetween; and   a lateral thin film load transistor including a sidewall gate insulation region on said sidewall portion of said gate electrode, between said top face and said bottom face and a lateral channel region on said sidewall pate insulation region between said top face and said bottom face such that said gate electrode controls the current in said lateral channel region between said top face and said bottom face, along a direction parallel to said substrate;   wherein said lateral channel region has first and second surfaces and contacts said sidewall gate insulation region at said first surface, and further comprising:   an auxiliary gate including an auxiliary gate insulation region on said second surface of said lateral channel region and an auxiliary gate electrode on said auxiliary gate insulation region.   
     
     
       7. An SRAM cell according to claim 6 further comprising an insulation region on said substrate, and wherein said auxiliary gate electrode comprises an auxiliary gate electrode on said insulation region extending from said insulation region to overlie portions of said lateral channel region. 
     
     
       8. An SRAM cell according to claim 6 wherein said auxiliary gate electrode comprises at least one of doped polycrystalline silicon, silicide and metal. 
     
     
       9. A thin-film load transistor for a static random access memory (SRAM) cell including a driving transistor controlled by a controlling electrode on a substrate, the controlling electrode having a top face, a bottom face and a sidewall portion extending therebetween, the thin-film load transistor comprising: a sidewall gate insulation region on the sidewall portion of the controlling electrode between said top face and said bottom face; and   a lateral channel region on said sidewall gate insulation region between said top face and said bottom face such that the controlling electrode controls current in said lateral channel region between said top face and said bottom face, along a direction parallel to said substrate.   
     
     
       10. A thin-film load transistor for a static random access memory (SRAM) cell including a driving transistor controlled by a controlling electrode on a substrate, the controlling electrode having a top face, a bottom face and a sidewall portion extending therebetween, the thin-film load transistor comprising: a sidewall gate insulation region on the sidewall portion of the controlling electrode between said top face and said bottom face; and   a lateral channel region on said sidewall sate insulation region between said top face and said bottom face such that the controlling electrode controls current in said lateral channel region between said top face and said bottom face, along a direction parallel to said substrate;   wherein said lateral channel region has first and second surfaces and contacts said sidewall gate insulation region at said first surface, and further comprising:   an auxiliary gate including an auxiliary gate insulation region on said second surface of said lateral channel region and an auxiliary gate electrode on said auxiliary insulation region.   
     
     
       11. A load transistor according to claim 10 further comprising an insulation region on said substrate, and wherein said auxiliary gate electrode comprises an auxiliary gate electrode on said insulation region, extending from said insulation region to overlie portions of said lateral channel region.