Method for verifying electrically programmable non-volatile memory cells of an electrically programmable non-volatile memory device after programming

Abstract

A method for verifying an electrically programmable non-volatile memory cell of an electrically programmable memory device after programming, providing for accessing the memory cell after having submitted the same to at least a programming pulse by means of a sensing circuit, checking an output of the sensing circuit, and submitting said memory cell to further programming pulses if said output of the sensing circuit corresponds to a non-programmed memory cell. The checking an output of the sensing circuit is performed at a first instant of time which is anticipated of a prescribed time interval with respect to a second instant of time at which said output of the sensing circuit is checked in a normal read operation of the memory device, said prescribed time interval corresponding to a prescribed security margin of programming of the memory cell. (FIGS. 2 and 4).

I claim: 
     
       1. Method for verifying an electrically programmable non-volatile memory cell of an electrically programmable memory device after programming, providing for accessing the memory cell after having submitted the same to at least a programming pulse by means of a sensing circuit, checking an output of the sensing circuit, and submitting said memory cell to further programming pulses if said output of the sensing circuit corresponds to a non-programmed memory cell, characterized in that said checking an output of the sensing circuit is performed at a first instant of time which is anticipated of a prescribed time interval with respect to a second instant of time at which said output of the sensing circuit is checked in a normal read operation of the memory device, said prescribed time interval corresponding to a prescribed security margin of programming of the memory cell. 
     
     
       2. Method according to claim 1, characterized in that said accessing the memory cell provides for pre-setting a potential of a respective column of memory cells to which said memory cell belongs and selecting a row of memory cells to which said memory cell belongs. 
     
     
       3. Method according to claim 2, characterized by providing for comparing a current sunk by said memory cell with a reference current sunk by a reference memory cell in a prescribed programming state. 
     
     
       4. Method according to claim 3, characterized in that said reference memory cell is a non-programmed memory cell. 
     
     
       5. Method according to claim 4, characterized in that said accessing the memory cell also provides for pre-setting a potential of a reference column of reference memory cells, said reference memory cell belonging to said row of memory cells to which said memory cell belongs. 
     
     
       6. Method according to claim 5, characterized in that said column of memory cells and said reference column of reference memory cells are pre-set at a same potential. 
     
     
       7. Method according to any one of the preceding claims, characterized in that said checking an output of the sensing circuit comprises memorizing said output at said first instant of time instead of at said second instant of time. 
     
     
       8. Method according to any one of the preceding claims, characterized in that said first instant of time and said second instant of time varies according to a conductivity of said memory cell. 
     
     
       9. Method according to claim 8, characterized in that said prescribed time interval depends on the conductivity of said memory cell. 
     
     
       10. Method according to claim 9, characterized in that said prescribed time interval is longer the higher the conductivity of said memory cell. 
     
     
       11. A method for verifying an electrically programmable non-volatile memory cell of an electrically programmable memory device after programming, the method comprising the steps of: (a) submitting the memory cell to one or more programming pulses;   (b) checking an output of the memory cell at a first instant of time that is a prescribed time interval before a second instant of time at which the output of the memory cell is checked in a normal read operation of the memory device; and   (c) submitting the memory cell to further programming pulses if the output of the memory cell corresponds to the output of a non-programmed memory cell.   
     
     
       12. The method of claim 11, wherein the step of checking includes the further steps of: (a) presetting a potential of a respective column of memory cells to which the memory cell belongs; and   (b) selecting a row of memory cells to which the memory cell belongs.   
     
     
       13. The method of claim 12, wherein the step of checking includes comparing a current sunk by said memory cell with a reference current sunk by a reference memory cell in a prescribed programmed state. 
     
     
       14. The method of claim 13, wherein the reference memory cell is a non-programmed memory cell. 
     
     
       15. The method of claim 14, wherein the step of checking the output of the memory cell includes the step of presetting a potential of a reference column of reference memory cell wherein the reference memory cell belongs to the row of memory cells to which the memory cell belongs. 
     
     
       16. The method of claim 15 wherein the column of memory cells and the reference column of reference memory cells are preset at the same potential. 
     
     
       17. The method of claim 11, wherein the step of checking the output of the memory cell comprises storing the output at the first instant of time instead of at the second instant of time. 
     
     
       18. The method of claim 11, wherein the first instant of time and the second instant of time vary according to a conductivity of the memory cell. 
     
     
       19. The method of claim 18, wherein the prescribed time interval depends on the conductivity of the memory cell. 
     
     
       20. The method of claim 19, wherein the prescribed time interval is longer the higher the conductivity of the memory cell. 
     
     
       21. Apparatus for verifying an electrically programmable non-volatile memory cell of an electrically programmable memory device after programming, comprising: (a) a generator of voltage pulses for submitting the memory cell to one or more programming pulses;   (b) electrical instrumentation for checking an output of the memory cell at a first instant of time that is a prescribed time interval before a second instant of time at which the output of the memory cell is checked in a normal read operation of the memory device; and   (c) a generator of voltage pulses for submitting the memory cell to further programming pulses if the output of the memory cell corresponds to the output of a non-programmed programmed memory cell.   
     
     
       22. Apparatus of claim 21, wherein electrical instrumentation for checking includes: (a) a voltage source for presetting a potential of a respective column of memory cells to which the memory cell belongs; and   (b) electrical instrumentation for selecting a row of memory cells to which the memory cell belongs.   
     
     
       23. Apparatus of claim 22, wherein electrical instrumentation for checking includes a comparator for comparing a current sunk by the memory cell with a reference current sunk by a reference memory cell in a prescribed programmed state. 
     
     
       24. Apparatus of claim 23, wherein the reference memory cell is a non-programmed memory cell. 
     
     
       25. Apparatus of claim 24, wherein electrical instrumentation for checking the output of the memory cell includes means of pre-setting a potential of a reference column of reference memory cell wherein the reference memory cell belongs to the row of memory cells to which the memory cell belongs. 
     
     
       26. Apparatus of claim 25 wherein the column of memory cells and the reference column of reference memory cells are preset at the same potential. 
     
     
       27. Apparatus of claim 21, wherein electrical instrumentation for checking the output of the memory cell comprises storing the output at the first instant of time instead of at the second instant of time. 
     
     
       28. Apparatus of claim 21, wherein the first instant of time and the second instant of time vary according to a conductivity of the memory cell. 
     
     
       29. Apparatus of claim 28, wherein the prescribed time interval depends on the conductivity of the memory cell. 
     
     
       30. Apparatus of claim 29, wherein the prescribed time interval is longer the higher the conductivity of the memory cell. 
     
     
       31. A circuit for verifying electrically programmable non-volatile memory cells of an electrically programmable non-volatile memory device after programming, including: (a) a voltage source for submitting the memory cell to one or more programming pulses;   (b) a sensing circuit for accessing the status of the memory cell;   (c) a timing signal generator for generating a timing signal at a time that is a prescribed time interval before the time at which the output of the sensing circuit is checked in a normal read operation of the memory device; and   (d) a voltage source for submitting the memory cell to further programming pulses if the output of the sensing circuit corresponds to the output of a non-programmed memory cell.   
     
     
       32. The timing generator of claim 31, comprising: (a) a timing block that generates a precharge signal;   (b) a control signal generator that receives the precharge signal and generates two control signals similar to the precharge signal except for slight activation delays;   (c) a voltage generator that generates two analog voltages with values depending upon current sunk by a transistor identical to and biased substantially the same way as the memory cell and a reference memory cell;   (d) an intermediary timing circuit that receives the precharge signal, one of the control signals, and one of the analog voltages and generates an intermediary time signal similar to the precharge signal but having longer duration, variable according to one of the analog voltages; and   (e) a final timing circuit that receives the precharge signal, the two analog voltages, one of the two control signals, and the intermediary time signal and generates the timing signal that has a time duration variable according to the time duration of the intermediary time signal and a falling edge with a slope at least partially variable according to the value of one of the analog voltages.   
     
     
       33. The circuit of claim 31, where the timing signal initiates equalizing voltages of a bit line attached to a memory cell and a bit line attached to a reference memory cell. 
     
     
       34. The circuit of claim 31, where the timing signals initiate storage of the memory cell bit line voltage and the reference memory cell bit line voltage. 
     
     
       35. The circuit of claim 31 where the memory cell bit line voltage and the reference memory cell bit line voltages are stored in a latch. 
     
     
       36. The circuit of claim 35 wherein a comparator receives voltages stored in the latch and generates an output voltage which is one value if the memory cell voltage is larger than the reference memory cell voltage and another value if the reference memory cell voltage is larger than the memory cell voltage. 
     
     
       37. The circuit of claim 36 including means for measuring the output voltage of the comparator. 
     
     
       38. The circuit of claim 37 wherein the means for measuring the output voltage of the comparator includes an oscilloscope. 
     
     
       39. The circuit of claim 37 wherein the means for measuring the output voltage of the comparator includes a memory programmer. 
     
     
       40. The circuit of claim 31 wherein the means for generating the time signals can be modulated according to the conductivity of the memory cells.