3V/5V input buffer

Abstract

An input buffer capable of operating at a first power supply voltage level or a second power supply voltage level with the operating voltage level selectable during manufacture. At least one shortable transistor is disposed between the power supply voltage input and a buffer circuit which is connected between an input and an output of the buffer circuit. When the first voltage is the intended operating voltage the at least one shortable transistor is shorted. The first operating voltage level meets the requirements of a CMOS device and the second operating voltage level meets the requirements of a TTL device. The shortable transistor can be either a p-channel or an n-channel transistor and the short can be done by a metal layer short, a polysilicon short, a depletion implant, or with vias during manufacture. Transistors in the buffer circuit are sized to provide an acceptable TTL device level trip point when the input buffer is operated at 5 volts and which also provides an acceptable CMOS device level trip point when the input buffer is operated at 3 volts. Transistors in the buffer circuit are provided to turn OFF the input buffer at the direction of an external circuit.

What I claim is: 
     
       1. An input buffer capable of operating at a first supply voltage or a second supply voltage with the operating voltage level selectable during manufacture, comprising: a power supply voltage input terminal;   a buffer circuit connected between a signal input terminal and a signal output terminal; and   at least one transistor connected between the power supply voltage input terminal and the buffer circuit, wherein a direct electrical connection is formed between the source and drain terminals of at least one of said transistor so as to short the at least one transistor when the first supply voltage is the intended operating voltage.   
     
     
       2. The input buffer of claim 1, wherein said buffer circuit further comprises: a first transistor; and   a second transistor wherein said first transistor and said second transistor are sized to provide a trip point appropriate for use at the second supply voltage, said first and said second transistors being connected in a series conduction path, a first node in said series conduction path between said first and said second transistors being connected to said signal output terminal.   
     
     
       3. The input buffer of claim 2, wherein said second supply voltage is the TTL device voltage level and the trip point is the trip point appropriate for the TTL device voltage level requirement. 
     
     
       4. The input buffer of claim 3, wherein said second supply voltage is approximately 5 volts. 
     
     
       5. The input buffer of claim 4, wherein said trip point is approximately 1.4 volts. 
     
     
       6. The input buffer of claim 2, wherein said first supply voltage is the CMOS device voltage level. 
     
     
       7. The input buffer of claim 6, wherein said first supply voltage is approximately 3 volts. 
     
     
       8. The input buffer of claim 7, wherein the trip point changes when the operating voltage changes from the second supply voltage to the first supply voltage. 
     
     
       9. The input buffer of claim 8, wherein the changed trip point is appropriate for the CMOS device voltage level requirements. 
     
     
       10. The input buffer of claim 9, wherein the changed trip point is approximately 1.2 volts. 
     
     
       11. The input buffer of claim 1, wherein the at least one transistor is shorted with a metal layer. 
     
     
       12. The input buffer of claim 1, wherein the at least one transistor is shorted with a depletion implant. 
     
     
       13. The input buffer of claim 2, wherein said buffer circuit further comprises third and fourth transistors to turn OFF the input buffer, said third transistor being connected in said series conduction path, said fourth transistor is connected in parallel with said second transistor the control terminals of said third and said fourth transistors being connected to a chip enable signal terminal. 
     
     
       14. The input buffer of claim 2, wherein the control terminals of said first and said second transistors are connected to said signal input terminal. 
     
     
       15. A method of manufacturing an input buffer unit capable of operating at a first supply voltage or a second supply voltage, the first supply voltage being lower than the second supply voltage, the operating voltage level at which the input buffer unit is to operate being selectable during manufacture, the method comprising the steps of: providing a buffer circuit, the buffer circuit having a signal input terminal, a signal output terminal, and a power terminal;   connecting the at least one transistor between the power terminal of the buffer circuit and a power supply voltage input terminal of the buffer unit;   determining whether the buffer unit is to operate at the first supply voltage or the second supply voltage; and   forming a direct electrical connection across at least one transistor so as to short the at least one transistor, if the buffer unit is to operate at the first supply voltage.   
     
     
       16. The method of claim 15, further comprising the step of providing a first transistor and a second transistor, said first and said second transistors being connected in a series conduction path, a first node in said series conduction path between said first and said second transistors being connected to said signal output terminal, wherein said first and said second transistors are sized to provide a trip point appropriate for use at the second supply voltage. 
     
     
       17. The input buffer of claim 16, wherein the control terminals of said first and said second transistors are connected to said signal input terminal. 
     
     
       18. The method of claim 16, wherein said second voltage is the TTL device voltage level and the trip point is the trip point appropriate for the TTL device voltage level requirement. 
     
     
       19. The method of claim 18, wherein said second supply voltage is approximately 5 volts. 
     
     
       20. The method of claim 19, wherein said trip point is approximately 1.4 volts. 
     
     
       21. The method of claim 16, wherein said first supply voltage is the CMOS device voltage level. 
     
     
       22. The input buffer of claim 21, wherein said first supply voltage is approximately 3 volts. 
     
     
       23. The method of claim 19, wherein the trip point changes when the operating voltage is changed from the second supply voltage to the first supply voltage. 
     
     
       24. The method of claim 20, wherein the changed trip point is appropriate for the CMOS device voltage level requirements. 
     
     
       25. The method of claim 24, wherein the changed trip point is approximately 1.2 volts. 
     
     
       26. The method of claim 15, further comprising the step of shorting the at least one transistor with a metal layer. 
     
     
       27. The method of claim 15, further comprising the step of shorting the at least one transistor with a depletion implant. 
     
     
       28. The method of claim 16, further comprising the step of providing third and fourth transistors to turn OFF the input buffer, said third transistor being connected in said series conduction path, said fourth transistor is connected in parallel with said second transistor the control terminals of said third and said fourth transistors being connected to a chip enable signal terminal.