Circuitry and method for simultaneously transmitting voice and data information

Abstract

Circuitry, and an associated method, for permitting simultaneous transmission of multiple forms of information, such as that generated during operation of a multi-media communication device. Signal bits of the different forms of information are together mapped onto symbols of a multi-level, multi-phase modulation symbol set. Transmission of signals representative of the symbols are transmitted, thereby to effectuate the simultaneous transmission of the multiple forms of information.

What is claimed is: 
     
       1. A communication device for simultaneously transmitting isochronous data representative of isochronous information and asynchronous data representative of asynchronous information upon a communication channel, said communication device comprising: an isochronous information bit generator coupled to receive the isochronous information, said isochronous information bit generator for generating isochronous bits indicative of the isochronous information;   an asynchronous information bit generator coupled to receive the asynchronous information, said asynchronous information bit generator for generating asynchronous bits indicative of the asynchronous information;   a mapper coupled to receive the isochronous bits and the asynchronous bits, said mapper for selectively mapping the isochronous and asynchronous bits, respectively, together onto symbols of a multi-level modulation symbol set, the symbols of the multilevel symbol set onto which the isochronous and asynchronous bits are mapped dependent upon values of the isochronous and asynchronous bits received by said mapper and forming the isochronous and asynchronous data; and   a transmitter coupled to receive the symbols onto which the isochronous and asynchronous bits are mapped by said mapper, said transmitter for transmitting the symbols, thereby to simultaneously transmit the isochronous and asynchronous data upon the communication channel.   
     
     
       2. In a communication system having a transmitting station and a receiving station, a combination with the transmitting station of transmit circuitry for simultaneously transmitting isochronous and asynchronous data upon a communication channel to the receiving station, said circuitry comprising: an isochronous information bit generator coupled to receive the isochronous information, said isochronous information bit generator for generating speech bits indicative of the isochronous information;   an asynchronous information bit generator coupled to receive the asynchronous information, said asynchronous information bit generator for generating asynchronous bits indicative of the asynchronous information;   a signal allocator having at least one input port selectively coupled to receive the asynchronous bits and the isochronous bits, said signal allocator for forming an allocated signal by selectively combining the received asynchronous bits and the received isochronous bits;   a mapper selectively coupled to receive the allocated signal, said mapper for mapping the allocated signal onto symbols of a multi-level modulation symbol set, the symbols of the multi-level symbol set onto which the allocated signal is mapped are dependent upon values of the isochronous and asynchronous bits within the allocated signal; and   a transmitter coupled to receive the symbol onto which the allocated signal is mapped by said mapper, said transmitter for transmitting the symbol forming the isochronous and asynchronous data upon the communication channel.   
     
     
       3. In the communication system of claim 2, a combination with the receiving station of receive circuitry for recovering the isochronous and asynchronous data formed of the symbol transmitted by said transmitter upon the communication channel, said receive circuitry comprising: a receiver tunable to the communication channel, said receiver for receiving the symbol transmitted by the transmitter and for forming a receive signal indicative thereof;   a mapper coupled to receive the receive signal formed by said receiver, said mapper for mapping the symbol of which the receive signal is indicative into an allocated signal;   a signal deallocator for separating the allocated signal into the isochronous bits and the asynchronous bits representing the isochronous and asynchronous data; and   a decoder coupled to receive the isochronous and asynchronous bits, respectively, said decoder for decoding the isochronous and asynchronous bits, thereby to recover the isochronous and asynchronous data therefrom.   
     
     
       4. In a transmitter operable to transmit speech data representative of isochronous information and asynchronous data representative of asynchronous information upon a communication channel, an improvement of information-combining circuitry for forming a combined signal which, when transmitted, permits simultaneous transmission of the isochronous data and asynchronous data upon the communication channel, said information-combining circuitry comprising: a signal allocator having at least one input port selectively coupled to receive signals representative of the isochronous data and signals representative of the asynchronous data, said signal allocator for forming an allocated signal of values responsive to values of the signals representative of the isochronous data and the signals representative of the asynchronous data selectively coupled to be received thereat; and   a mapper coupled to receive the allocated signal, said mapper for mapping selected portions of the allocated signal onto symbols of a multi-symbol modulation symbol set, the symbols of the multi-symbol set onto which the selected portions of the allocated signal are mapped dependent upon values of the allocated signal, the symbols onto which the portions of the allocated isochronous data and the asynchronous data signal are mapped forming the combined signal.   
     
     
       5. The circuitry of claim 4 further comprising an isochronous information bit generator coupled to receive the isochronous information, said isochronous information bit generator for generating isochronous bits indicative of the isochronous information and wherein the signals representative of the isochronous data received at a first input port of said at least one input port of said signal allocator comprises the isochronous bits. 
     
     
       6. The circuitry of claim 5 wherein said isochronous information signal bit generator comprises a digitizer coupled to receive the isochronous information, said digitizer for digitizing the isochronous information and for forming digitized isochronous signals, a coder coupled to receive the digitized isochronous signals, said coder for coding the digitized isochronous signals and for forming coded isochronous signals responsive thereto, an interleaver coupled to receive the coded isochronous signals, said interleaver for interleaving the coded isochronous signals and for forming interleaved isochronous signals responsive thereto, and a scrambler coupled to receive the interleaved signals, said scrambler for scrambling the interleaved signals and for forming scrambled isochronous signals, the scrambled isochronous signals forming the isochronous signal bits. 
     
     
       7. The circuitry of claim 4 further comprising a asynchronous information bit generator coupled to receive the asynchronous information, said asynchronous information bit generator for generating asynchronous bits indicative of the asynchronous information and wherein the signals representative of the asynchronous data received at a second input port of said signal allocator input port comprises the asynchronous bits. 
     
     
       8. The circuitry of claim 7 wherein said asynchronous information signal bit generator comprises a digitizer coupled to receive the asynchronous information, said digitizer for digitizing the asynchronous information and for forming digitized asynchronous signals, a coder coupled to receive the digitized asynchronous signals, said coder for coding the digitized asynchronous signals and for forming coded asynchronous signals responsive thereto, an interleaver coupled to receive the coded asynchronous signals, said interleaver for interleaving the coded asynchronous signals and for forming interleaved asynchronous signals responsive thereto, and a scrambler coupled to receive the interleaved asynchronous signals, said scrambler for scrambling the interleaved asynchronous signals and for forming scrambled asynchronous signals, the scrambled asynchronous signals forming the asynchronous signal bits. 
     
     
       9. The circuity of claim 4 wherein said signal allocator comprises a multiplexer for multiplexing the signals representative of the speech information and the signals representative of the asynchronous information, said at least one input port comprises a first input port and a second input port formed of a first input terminal and a second input terminal, respectively, of said multiplexer, and wherein said mapper is coupled to receive the signals representative of the isochronous data and the asynchronous data once multiplexed together by said multiplexer. 
     
     
       10. The circuity of claim 4 wherein the multi-symbol modulation symbol set onto which the symbols thereof said mapper maps the signals representative of the isochronous data and the asynchronous data comprises a multi-phase modulation symbol set. 
     
     
       11. The circuitry of claim 4 wherein the multi-symbol modulation symbol set onto which the symbols thereof said mapper maps the signals representative of the isochronous data and the asynchronous data comprises a multi-level modulation symbol set. 
     
     
       12. The circuitry of claim 4 wherein the symbols of the multi-level symbol set are represented by complex valued numbers represented by a first real-valued component and a second real-valued component. 
     
     
       13. The circuitry of claim 12 wherein the first real-valued component is formed of a selected combination of values of the signal representative of the isochronous information. 
     
     
       14. The circuitry of claim 12 wherein the second real-valued component is formed of a selected combination of values of the signal representative of the asynchronous information. 
     
     
       15. The circuitry of claim 4 wherein the asynchronous information comprises textual information and wherein a second input port receives signals representative of the textual information. 
     
     
       16. The circuity of claim 4 wherein the transmitter forms a portion of a multi-media communication system, wherein the asynchronous information comprises diagrammatic information and wherein said at least one input port of the signal allocator receives signals representative of the diagrammatic information. 
     
     
       17. The circuitry of claim 4 wherein the transmitter forms a portion of a multi-mode communication system, wherein the asynchronous information comprises control information, and wherein said at least one input port of the signal allocator receives signals representative of the control information. 
     
     
       18. The circuitry of claim 4 wherein the asynchronous information comprises a first-type asynchronous information portion and a second-type asynchronous information portion, wherein said at least one input port of said signal allocator comprises a first input port, a second input port, and a third input port, the first input port coupled to receive the signals representative of the isochronous data, the second input port for receiving the first-type asynchronous information portion of the signals representative of the asynchronous data, and the third input port for receiving the second-type asynchronous information portion of the signals representative of the asynchronous data. 
     
     
       19. The circuitry of claim 4 further comprising a controller coupled to receive indications of rates at which the signals representative of the isochronous information and at which the signals representative of the asynchronous information are applied to said signal allocator, said controller further coupled to said signal allocator, said controller for controlling the coupling of said signal allocator to receive the signals representative of the isochronous information and the asynchronous information, respectively, responsive, at least in part upon the rates of which the indications thereof are received at said controller. 
     
     
       20. The circuitry of claim 4 further comprising a controller coupled to receive indications of rates at which the signals representative of the isochronous information and at which the signals representative of the asynchronous information are applied to said signal allocator, said controller further coupled to said signal allocator, said controller for controlling the coupling of said signal allocator to receive the signals representative of the isochronous information and the asynchronous information, respectively, responsive, at least in part upon indications of channel conditions of the communication channel. 
     
     
       21. A method for simultaneously transmitting isochronous data representative of isochronous information and asynchronous data representative of asynchronous information upon a communication channel, said method comprising the steps of: generating isochronous bits indicative of the isochronous information;   generating asynchronous bits indicative of the asynchronous information;   selectively combining the isochronous and asynchronous bits into an allocated signal;   selectively mapping the allocated signal onto symbols of a multi-level modulation symbol set, the symbols of the multi-level symbol set onto which the allocated signal is selectively mapped dependent upon values of the isochronous and asynchronous bits and forming the isochronous asynchronous data; and   transmitting the symbol containing the isochronous and asynchronous data upon the communication channel.