Semiconductor memory device and high-voltage switching circuit

Abstract

A semiconductor memory device comprises an array of electrically rewritable memory cells which are arranged in a matrix, erasing section for applying an erasing voltage to the memory cells to effect erasing, and writing section for applying a writing voltage to the memory cells to effect writing, wherein in the erasing section and writing section, either MOS transistors to which a voltage higher than the erasing voltage and writing voltage is applied or MOS transistors which transfer a voltage higher than the erasing voltage and writing voltage contain MOS transistors which are in a weak inversion state or an inversion state with their substrate bias voltage, gate voltage and source voltage at 0 V.

What is claimed is: 
     
       1. A semiconductor memory device comprising: a memory cell array where memory cells are arranged in a matrix, said memory cells forming a plurality of memory cell groups;   block select circuits for selecting memory cell blocks containing said plurality of memory cell groups; and   means for bringing all of said block select circuits into a block-selected state in a stand-by condition.   
     
     
       2. A semiconductor memory device according to claim 1, wherein said block select circuits contains voltage conversion circuits, each composed of a block address decoder and a MOS transistor of a first-conductivity type connected to said block address decoder. 
     
     
       3. A semiconductor memory device according to claim 2, further comprising a block control circuit that receives the outputs of said block select circuits and controls said memory-cell blocks, wherein said block control circuit is a voltage transfer circuit composed of the first-conductivity-type MOS transistor whose gate electrode is connected to said block select circuit.   
     
     
       4. A semiconductor memory device comprising: an array of electrically rewritable memory cells which are arranged in a matrix, said memory cells forming a plurality of memory cell groups;   erasing means for applying an erasing voltage to said memory cells to effect erasing;   writing means for applying a writing voltage to said memory cells to effect writing; and   block select circuits for selecting memory cell blocks containing said plurality of memory cell groups, wherein in said erasing means and writing means, MOS transistors to which a voltage higher than said erasing voltage and writing voltage is applied or transferred are in a weak inversion state or an inversion state with their substrate bias voltage, gate voltage and source voltage at 0 V, and said erasing means and writing means contain means for bringing all of said block select circuits into a block-selected state in a stand-by condition.     
     
     
       5. A semiconductor memory device according to claim 4, wherein said block select circuits contains voltage conversion circuits, each composed of a block address decoder and a MOS transistor of a first-conductivity type connected to said block address decoder. 
     
     
       6. A semiconductor memory device according to claim 5, further comprising a block control circuit that receives the outputs of said block select circuits and controls said memory-cell blocks, wherein said block control circuit is a voltage transfer circuit composed of the first-conductivity-type MOS transistor whose gate electrode is connected to said block select circuit.   
     
     
       7. A semiconductor memory device comprising: a memory cell array in which memory cells are arranged in a matrix; and   memory-cell control means for controlling said memory cells, wherein said memory cell control means contains a switching circuit comprising a charge transfer circuit where the source electrode of a first MOS transistor is connected to the drain electrode of a second MOS transistor and the gate electrode of said first MOS transistor is connected to the gate electrode of said second MOS transistor and   a bias circuit that applies a bias voltage to the source electrode of said second MOS transistor and the drain electrode Os said second MOS transistor so as to electrically disconnect the drain electrode of said first MOS transistor from the source of said second MOS transistor in case that said switching circuit is unselected and that does not apply said bias voltage to the source electrode of said first MOS transistor and the drain electrode of said second MOS transistor so as to electrically connect the drain electrode of said first MOS transistor to the source electrode of said second MOS transistor in case that said switching circuit is selected, said bias circuit being deactivated in a stand-by condition.