Input/output device with self-test capability in an integrated circuit

Abstract

An input/output device in an integrated circuit including a plurality of input buffer units for buffering a data signal provided through each input pin or a test data signal to output it to a core logic, and outputting an inverted test data signal, according to a first test signal; a plurality of output buffer units for selecting and buffering the data signal provided from the core logic or the test data signal, providing the buffered data to each output pin, and outputting an inverted test data signal, according to the first test signal; and a plurality of input/output buffer units for buffering the data signal provided from the core logic or the test data signal to output it to each input/output pin and output an inverted test data signal, and buffering the data signal inputted through each input/output pin to output it to the core logic.

What is claimed is: 
     
       1. An input/output device in an integrated circuit having a core logic and a plurality of input pins, input/output pins, and output pins, comprising: a plurality of input buffer units for buffering an input data signal provided through each input pin or a test data signal to output it to the core logic, and for outputting an inverted second test data signal according to inputting of a first test signal;   a plurality of output buffer units for selecting and buffering a data signal provided from the core logic or the test data signal to output it to each output pin, and inverting and outputting the inverted second test data signal according to inputting of the first test signal; and   at least one input/output buffer units for selecting and buffering one of (1) the data signal provided from the core logic or the test data signal to output it to each input/output pin and (2) the input data signal inputted through each input/output pin or the test data signal to output it to the core logic, and for inverting and outputting the inverted second test data signal according to the first test signal.   
     
     
       2. The device according to claim 1, wherein the plurality of input buffer units each includes: an input buffer having an input terminal connected to corresponding input pin and an output terminal of which is connected to the core logic; and   an invertor being enabled by the first test signal, for inverting the input test data signal provided from the input buffer and outputting the inverted second test data signal.   
     
     
       3. The device according to claim 1, wherein the plurality of input buffer units are sequentially arranged according to an order of each input pin, and an output terminal of an invertor included in each input buffer unit is connected to an input terminal of an input buffer included in a next sequential input buffer unit. 
     
     
       4. The device according to claim 1, wherein the plurality of output buffer units each includes: a multiplexer being controlled according to the first test signal for selecting an input test data signal during a test regarding direct current characteristics;   an output buffer for buffering an output signal of the multiplexer and outputting the buffered signal to corresponding output pin; and   an invertor being enabled by the first test signal for inverting the output signal of the multiplexer and outputting the inverted second test data signal.   
     
     
       5. The apparatus according to claim 4, wherein the plurality of output buffer units are sequentially arranged according to an order of each output pin, a multiplexer of the first output buffer unit receives the second test data signal provided from the last input buffer unit of the plurality of input buffer units, and an output signal of the invertor included in one output buffer unit is inputted to the multiplexer included in the next output buffer unit. 
     
     
       6. The device according to claim 1, wherein the plurality of input/output buffer units, in testing direct current characteristics, each includes: a first multiplexer being controlled according to the first test signal for selecting an input test data signal;   a second multiplexer being controlled according to the first test signal for selecting a second test signal;   an output buffer for buffering the output signal of the first multiplexer and outputting the buffered signal to corresponding output pin, according to the output signal of the second multiplexer;   an input buffer for buffering the output signal of the output buffer or an input signal; and   an invertor for inverting the output signal of the input buffer and outputting the second test data signal.   
     
     
       7. The device according to claim 6, wherein the plurality of the input/output buffer units are sequentially arranged according to an order of each input/output pin, a first multiplexer of the first input buffer receives the second test data signal provided from the last output buffer unit of the plurality of the output buffer units, an output signal of the invertor included in one input/output buffer unit is inputted to the first multiplexer included in the next input/output buffer unit, and the last input/output buffer unit does not include any invertor. 
     
     
       8. An input/output device in an integrated circuit having a core logic and a plurality of input pins, input/output pins and output pins, comprising: a plurality of input buffer units that buffers a first signal provided through each input pin to output it to the core logic and that outputs a second signal based on a received first test signal; and   a plurality of input/output buffer units that selects and buffers the first signal provided from the core logic to output it to a corresponding one of the input/output pins or buffers the first signal provided by the corresponding one of the input/output pins to output it to the core logic, and that outputs the second signal based on the received first test signal, wherein the second signal is output to a subsequent buffer unit except for a final buffer unit.   
     
     
       9. The input/output device of claim 8, wherein a two part test signal provides a short/open test of the input/output device. 
     
     
       10. The input/output device of claim 8, wherein a two cycle test signal provides direct current characteristics test of the input/output device. 
     
     
       11. The input/output device of claim 8, further comprising a plurality of output buffer units that selects and buffers the first signal provided from the core logic to output it to a corresponding one of the output pins and that outputs the second signal based on the received first test signal. 
     
     
       12. The input/output device of claim 8, wherein each of the buffer units is directly coupled to a subsequent buffer unit except for the final buffer unit. 
     
     
       13. The input/output device of claim 8, wherein each buffer unit includes a logic circuit to generate the second signal. 
     
     
       14. The input/output device of claim 8, wherein each buffer unit includes a logic gate to generate the second signal, wherein the logic gate is an inverter. 
     
     
       15. The input/output device of claim 8, wherein the first signal is an input data signal or a first test signal and the second signal is a second test data signal.