Computer system with multi-buffer data cache for prefetching data having different temporal and spatial localities

Abstract

A computer system including a multi buffer data cache and method of caching data based on predicted temporal and spatial localities. A processor operates on operands under instruction control, the operands being stored in a main memory. The processor is coupled to the main memory via a data cache for prefetch and storage of operands referenced by the instructions. The data cache comprises an S-buffer for storing operands with strong temporal locality, and a P-buffer for storing operands with strong spatial locality. A control unit connected to the processor, the buffers and the main memory, determines what type of locality is involved in the operand referenced, based on whether the instruction accesses the main memory in a direct or indirect addressing mode as determined by a decoder unit of the processor, and governs operation of the buffer associated with the type of locality determined. Data references may be classified into a plurality of groups, which may include data references to stack data or global variable data, on the basis of predicted statistical associations of localities of the data references. The processor may include a stack pointer register and the computer system may identify requests using the indirect addressing mode based on the stack pointer register.

I claim: 
     
       1. A computer system comprising: a processor for operating on operands under control of instructions;   a main memory for storage of the operands;   a data cache between the main memory and the processor for prefetch and storage of specific ones of the operands referenced by the instructions; wherein the data cache comprises:     an S-buffer for storage of a plurality of the operands with strong temporal locality;   a P-buffer for storage of a plurality of the operands with strong spatial locality;   a control unit connected to the processor, the S-buffer, the P-buffer, and the main memory, for determining whether the operand referenced involves either the strong temporal locality or the strong spatial locality, and for thereupon controlling operation of a particular one of the buffers associated with the type of locality determined.   
     
     
       2. The system of claim 1, wherein the control unit is operative to determine the strong temporal locality or the strong spatial locality being involved on the basis of an addressing mode of the main memory. 
     
     
       3. The system of claim 2, wherein the processor comprises a decode unit connected to the control unit and operative to discriminate between a direct addressing mode and an indirect addressing mode for informing the control unit of which of the address modes is involved. 
     
     
       4. A method of caching data in a computer system with: a processor for operating on operands under control of instructions;   a main memory for storage of the operands;   a data cache between the main memory and the processor for prefetch and storage of specific ones of the operands referenced by the instructions; wherein the data cache comprises:     an S-buffer for storage of a plurality of the operands with strong temporal locality;   a P-buffer for storage of a plurality of the operands with strong spatial locality; wherein the method comprises:     determining whether the operand referenced involves either the strong temporal locality or the strong spatial locality; and   controlling operation of a particular one of the buffers associated with the type of locality determined.   
     
     
       5. A computer system, comprising: a processor for operating on operands under control of instructions;   a main memory storing the operands;   a data cache between the main memory and the processor for storage of specific ones of the operands referenced by the instructions, said data cache including an S-buffer for storage of a plurality of the operands with strong temporal locality and a P-buffer for storage of a plurality of operands with strong spatial locality, each of the P-buffer and the S-buffer including a plurality of blocks;   a control unit communicating with the processor, the cache and the main memory;   the processor further including means, upon detection of an operand reference in an instruction, for determining the addressing mode and the registers used and communicating the addressing modes and registers so determined to the control unit, the control unit including means for categorizing a referenced operand as an S-reference corresponding to the S-buffer or P-reference corresponding to the P-buffer, from the addressing mode and registers determined by the processor,   for checking both the S-buffer and the P-buffer for the presence of the referenced operand,   for, in the case of a referenced operand not being present in the P-buffer and the S-buffer, fetching the referenced operand from the main memory and storing the fetched reference in the respective buffer,   for not changing the S-buffer and P-buffer if (i) the referenced operand is an S-reference present in the S-buffer or in the P-buffer, and (ii) the referenced operand is a P-reference in the P-buffer,   for, in the case of a referenced operand being an S-reference present in the P-buffer, transferring the cache block corresponding to the S-reference from the P-buffer to the S-buffer, and marking the P-buffer cache block from which the operands were transferred as empty, and     for sequentially prefetching operands for the P-buffer but not for the S-buffer.   
     
     
       6. A method of handling data operands in a computer system having a processor, a main memory and a data cache having a plurality of cache blocks, said method comprising the steps of: allocating a first plurality of cache blocks as an S-buffer for storage of a plurality of the operands with strong temporal locality and a P-buffer for storage of a plurality of operands with strong spatial locality;   detecting an operand referenced in an instruction and determining the addressing mode and the registers used;   categorizing a referenced operand as an S-reference corresponding to the S-buffer or P-reference corresponding to the P-buffer from the determined addressing mode and registers;   checking both the S-buffer and the P-buffer for the presence of the referenced operand,   in the case of a referenced operand not being present in the P-buffer and the S-buffer, fetching the referenced operand from the main memory and storing the fetched reference in the respective buffer;   leaving the S-buffer and P-buffer unchanged if (i) the referenced operand is an S-reference present in the S-buffer or in the P-buffer, and (ii) the referenced operand is a P-reference in the P-buffer;   in the case of a referenced operand being an S-reference present in the P-buffer, transferring the cache block corresponding to the S-reference from the P-buffer to the S-buffer, and marking the cache block from which the operands were transferred as empty; and   sequentially prefetching operands for the P-buffer but not for the S-buffer.