CMOS interface for coupling a low voltage integrated circuit with devices powered at a higher supply voltage

Abstract

An interface circuit for coupling the output of an integrated circuit designed for a relatively low supply voltage to a circuit designed to operate at a higher supply voltage employs a cascoded architecture and makes use of two purposely derived reference voltages. The circuit comprises a level rising stage, an output buffer stage (off chip driver stage), an overdrive stage for the pull-up device of the output buffer and a drain follower stage, the pull-up element of which is driven by a second output node of the level rising stage and the pull-down element of which is driven by the inverted input data stream.

I claim: 
     
       1. An interface circuit for coupling an integrated circuit functioning at a first supply voltage (VCC1) to a node subject to voltage excursions of amplitude substantially equal to a second supply voltage (VCC2) higher than the first supply voltage of the integrated circuit, the interface circuit comprising: reference voltage generating means for generating a first reference voltage (Vref --  p) and a second reference voltage (Vref --  n);   a level lifting stage having a cascode structure comprising a first n-channel section comprising an n-channel cascoding transistor having a gate coupled to said second reference voltage (Vref --  n) and a second p-channel section comprising a p-channel cascoding transistor having a gate coupled to said first reference voltage (Vref --  p), said level lifting stage being driven by an input data signal (A) and by an inverted input data signal (AN) for producing respective first and second output signals (DF1 and DF2) both switching between the second supply voltage (VCC2) and a voltage defined by a difference between the second supply voltage (VCC2) and the second reference voltage (Vref --  p) plus a voltage drop (Vp) through a p-channel transistor of said second p-channel section;   at least one output buffer stage having a cascode structure and comprising an n-channel section comprising an n-channel cascoding transistor having a gate coupled to the first reference voltage (Vref --  n) and a p-channel section comprising a p-channel cascoding transistor having a gate coupled to the second reference voltage (Vref --  p), said at least one output buffer stage further comprising a p-channel pull-up device; and   an overdriving stage for the p-channel pull-up device of said at least one output buffer stage and comprising an n-channel diode functionally connected between a driving node of said p-channel pull-up device and the second output signal (DF2) of said level lifting stage, and a drain follower stage comprising a pull-up device driven by the first output signal (DF1) of said level lifting stage and a pull-down device driven by the inverted input signal (AN).   
     
     
       2. The interface circuit as defined in claim 1, wherein said drain follower stage comprises a p-channel section comprising a p-channel cascoding transistor having a gate coupled to the first reference voltage (Vref --  p) and an n-channel section comprising at least one n-channel diode. 
     
     
       3. The interface circuit as defined in claim 1, wherein said reference voltage generating means comprises means for generating the second reference voltage (Vref --  n) to be equal to the first supply voltage (VCC1). 
     
     
       4. The interface circuit as defined in claim 1, wherein said reference voltage generating means comprises: a bandgap cell for producing a basic reference voltage independent of the supply voltage;   an operational amplifier (OP AMP) in a non-inverting configuration and having an input connected to said bandgap cell for producing an output voltage (VMAX) proportional to the basic reference voltage for use as the second reference voltage (Vref --  n); and   a circuit having respective inputs for the second supply voltage (VCC2) and the output voltage (VMAX) produced by said operational amplifier and for producing as an output the first reference voltage (Vref --  p) to be equivalent to the difference between the second supply voltage (VCC2) and the output voltage (VMAX).   
     
     
       5. An interface circuit for coupling a circuit functioning at a first supply voltage (VCC1) to a node subject to voltage excursions of amplitude substantially equal to a second supply voltage (VCC2) higher than the first supply voltage, the interface circuit comprising: reference voltage generating means for generating a first reference voltage (Vref --  p) and a second reference voltage (Vref --  n);   a level lifting stage having a cascode structure comprising a first n-channel section comprising an n-channel cascoding transistor having a gate coupled to said second reference voltage (Vref --  n) and a second p-channel section comprising a p-channel cascading transistor having a gate coupled to said first reference voltage (Vref --  p), said level lifting stage being driven by an input data signal (A) and by an inverted input data signal (AN) for producing respective first and second output signals (DF1 and DF2) both switching between the second supply voltage (VCC2) and a voltage defined by a difference between the second supply voltage (VCC2) and the second reference voltage (Vref --  p) plus a voltage drop (Vp) through a p-channel transistor of said second p-channel section;   at least one output buffer stage having a cascode structure and comprising an n-channel section comprising an n-channel cascading transistor having a gate coupled to the first reference voltage (Vref --  n) and a p-channel section comprising a p-channel cascading transistor having a gate coupled to the second reference voltage (Vref --  p), said at least one output buffer stage further comprising a p-channel pull-up device; and   an overdriving stage for the p-channel pull-up device of said at least one output buffer stage and comprising an n-channel diode functionally connected between a driving node of said p-channel pull-up device and the second output signal (DF2) of said level lifting stage, and a drain follower stage comprising a pull-up device driven by the first output signal (DF1) of said level lifting stage and a pull-down device driven by the inverted input signal (AN), said drain follower stage comprising a p-channel section comprising a p-channel cascoding transistor having a gate coupled to the first reference voltage (Vref --  p) and an n-channel section comprising at least one n-channel diode.   
     
     
       6. The interface circuit as defined in claim 5, wherein said reference voltage generating means comprises means for generating the second reference voltage (Vref --  n) to be equal to the first supply voltage (VCC1). 
     
     
       7. The interface circuit as defined in claim 5, wherein said reference voltage generating means comprises: a bandgap cell for producing a basic reference voltage independent of the supply voltage;   an operational amplifier (OP AMP) in a non-inverting configuration and having an input connected to said bandgap cell for producing an output voltage (VMAX) proportional to the basic reference voltage for use as the second reference voltage (Vref --  n); and   a circuit having respective inputs for the second supply voltage (VCC2) and the output voltage (VMAX) produced by said operational amplifier and for producing as an output the first reference voltage (Vref --  p) to be equivalent to the difference between the second supply voltage (VCC2) and the output voltage (VMAX).   
     
     
       8. A bi-directional input/output (I/O) cell comprising: an output section comprising an interface circuit for coupling a circuit functioning at a first supply voltage (VCC1) to a node subject to voltage excursions of amplitude substantially equal to a second supply voltage (VCC2) higher than the first supply voltage, the interface circuit comprising:   reference voltage generating means for generating a first reference voltage (Vref --  p) and a second reference voltage (Vref --  n);   a level lifting stage having a cascode structure comprising a first n-channel section comprising an n-channel cascading transistor having a gate coupled to said second reference voltage (Vref --  n) and a second p-channel section comprising a p-channel cascoding transistor having a gate coupled to said first reference voltage (Vref --  p), said level lifting stage being driven by an input data signal (A) and by an inverted input data signal (AN) for producing respective first and second output signals (DF1 and DF2) both switching between the second supply voltage (VCC2) and a voltage defined by a difference between the second supply voltage (VCC2) and the second reference voltage (Vref --  p) plus a voltage drop (Vp) through a p-channel transistor;   at least one output buffer stage having a cascode structure and comprising an n-channel section comprising an n-channel cascading transistor having a gate coupled to said first reference voltage (Vref --  n) and a p-channel section comprising a p-channel cascading transistor having a gate coupled to the second reference voltage (Vref --  p), said at least one output buffer stage further comprising a p-channel pull-up device; and   an overdriving stage for the p-channel pull-up device of said at least one output buffer stage comprising an n-channel diode functionally connected between a driving node of said p-channel pull-up device and the second output signal (DF2) of said level lifting stage, and a drain follower stage comprising a pull-up device driven by the first output signal (DF1) of said level lifting stage and a pull-down device driven by the inverted input signal (AN); and   an input section connected to said output section, said input section capable of withstanding the second reference voltage (VCC2).   
     
     
       9. The bi-directional I/O cell as defined in claim 8, wherein said drain follower stage comprises a p-channel section comprising a p-channel cascoding transistor having a gate coupled to the first reference voltage (Vref --  p) and an n-channel section comprising at least one n-channel diode. 
     
     
       10. The bi-directional I/O cell as defined in claim 8, wherein said reference voltage generating means comprises means for generating the second reference voltage (Vref --  n) to be equal to the first supply voltage (VCC1). 
     
     
       11. The bi-directional I/O cell as defined in claim 8, wherein said reference voltage generating means comprises: a bandgap cell for producing a basic reference voltage independent of the supply voltage;   an operational amplifier (OP AMP) in a non-inverting configuration and having an input connected to said bandgap cell for producing an output voltage (VMAX) proportional to the basic reference voltage for use as the second reference voltage (Vref --  n); and   a circuit having respective inputs for the second supply voltage (VCC2) and the output voltage (VMAX) produced by said operational amplifier and for producing as an output the first reference voltage (Vref --  p) equivalent to the difference between the second supply voltage (VCC2) and the output voltage (VMAX).