FM-PM receivers with frequency deviation compression

Abstract

Signal processing apparatus (410) includes a phase-locked oscillator (200, 236, 310, 330, 390), having a closed loop with both forward (204) and feedback (206) paths, that is a part of a larger closed loop (438). The larger loop (438) is phase locked to the phase-locked oscillator (200, 236, 310, 330, 390) by a signal derived from the larger closed loop (438) that modulates the feedback path (206), and by an output frequency of the phase-locked oscillator (200, 236, 310, 330, 390) that is delivered to the larger loop (438). Modulating the feedback path (206) either adds pulses to the feedback path (206) or removes pulses, thereby causing irregularities in the flow of pulses. A low-pass filter (210) in the feedback path (206) obviates these irregularities, thereby also obviating incidental frequency modulation (IFM) in the output of the phase-locked oscillator (200, 236, 310, 330, 390). Frequency response limitation caused by the low-pass filter (210) is obviated by using the derived signal to modulate the forward path (204) substantially simultaneously with modulation of the feedback path (206).

What is claimed is: 
     
       1. Signal processing apparatus (410) which comprises means (420) for receiving a modulated signal, and means, comprising a closed loop (438), for producing the demodulated output of said modulated signal, the improvement which comprises: phase-locking oscillator means (270, 304, 318, 332, or 392), comprising a phase-locked loop (202) that is interposed into said closed loop and that includes both a forward path (204) and a feedback path (206), for phase locking an output frequency to a reference frequency;   frequency response limiting means, comprising a low-pass filter (210) that is interposed into said forward path, for restricting phase-locking frequency response of said phase-locking oscillator means;   means, comprising operative connection (230) of said output frequency to said closed loop, and comprising operative connection (268, 436) to said feedback path of a signal derived from said closed loop, for phase locking said closed loop; and   means, comprising operative connection (268) of said derived signal to said forward path, and comprising means (264) for varying a frequency in said forward path in response to said derived signal, for achieving said phase locking of said closed loop without frequency response restriction by said frequency response limiting means.   
     
     
       2. Signal processing apparatus (410) as claimed in claim 1 in which said operative connection (268, 436) of said derived signal to said feedback path (206) comprises: means, comprising a modulation oscillator (256), for generating a modulation frequency that is a function of said derived signal; and   D.C. modulator means (272, 306, 320, 334, 394), comprising said modulation oscillator, and being operatively connected to both said derived signal and said feedback path, for D.C. modulating said feedback path as an exact mathematical function of said modulation frequency.   
     
     
       3. Signal processing apparatus (410) as claimed in claim 2 in which said means (272, 306, 320, 394) for D.C. modulating said feedback path (206) as an exact mathematical function of said modulation frequency comprises frequency varying means (234, 348, or 398) for varying a frequency in said feedback path, and synchronizer means (254, 276, 322, or 400) for synchronizing said varying of said frequency in said feedback path with said modulation frequency. 
     
     
       4. Signal processing apparatus (410) as claimed in claim 2 in which said means (272, 306, 320) for D.C. modulating said feedback path (206) as an exact mathematical function of said modulation frequency comprises dual modulus divider means (234), being interposed into said feedback path, for dividing a frequency in said feedback path by dual moduli, and synchronizer means (254, 276, 322) for synchronizing changing of said moduli with said modulation frequency. 
     
     
       5. Signal processing apparatus (410) as claimed in claim 4 in which said synchronizer means (254, 276, 322) comprises a flip-flop (278, 280). 
     
     
       6. Signal processing apparatus (410) as claimed in claim 4 in which said apparatus further comprises: channelizing means, comprising said dual modulus divider means (234), comprising a variable modulus divider (244) that is interposed into said feedback path (206), and comprising a modulus controller (246) that is operatively connected to said dual modulus divider means and to said variable modulus divider, for channelizing said feedback frequency; and   preventing means, comprising said synchronizer means (276, 322), and comprising said synchronizer means being operatively connected to said dual modulus divider means and to said modulus controller, for preventing interference between said channelizing means and said D.C. modulator means (306, 320).   
     
     
       7. Signal processing apparatus (410) as claimed in claim 2 in which said apparatus further comprises: channelizing means (234, 244), being interposed into said feedback path (206), for channelizing a frequency in said feedback path; and   preventing means (246), being operatively connected to said modulation oscillator (256) and to said channelizing means, for preventing interference between said channelizing means and said D.C. modulator means (306, 320).   
     
     
       8. Signal processing apparatus is (410) as claimed in claim 1 in which said apparatus comprises means (234, 244), being operatively connected to said feedback path (206), for channelizing said output frequency without varying said reference frequency. 
     
     
       9. Signal processing apparatus (410) which comprises means (420) for receiving an angularly modulated signal, and means, comprising a first closed loop (438), for reducing modulation deviations of said angularly modulated signal, the improvement which comprises: a second closed loop (202), being interposed into said first closed loop, and having both a forward path (204) and a feedback path (206);   phase-locking means, comprising operative connection of said first and second closed loops, and comprising means (234, 256, 254, 276, 322, 400) for varying a frequency in said feedback path, for phase locking both of said closed loops;   frequency response limiting means (210), being interposed into said forward path, for limiting frequency response of said second closed loop; and   means, comprising means (212, 264) for varying a frequency in said forward path, for phase locking said closed loops without frequency response limitation by said frequency response limiting means.   
     
     
       10. Signal processing apparatus (410) as claimed in claim 9 in which both said phase-locking means and said operative connection thereof comprise: means (230) for deriving a signal from said first closed loop (438);   means, comprising a modulation oscillator (256) that is operatively connected to said derived signal, for producing a modulation frequency that is a function of said derived signal; and   means (234, 254), being operatively connected to said modulation oscillator and to said feedback path (206), for D.C. modulating said feedback path as an exact mathematical function of said modulation frequency.   
     
     
       11. Signal processing apparatus (410) as claimed in claim 10 in which said means (234, 254) for D.C. modulating said feedback path (206) as an exact mathematical function of said modulation frequency comprises: dual modulus divider means (234), being operatively connected to said modulation oscillator (256) and to said feedback path, for dividing a frequency in said feedback path by different moduli; and   synchronizer means (254, 276, 322, 400), being operatively connected to both said modulation oscillator and to said dual modulus divider means, for synchronizing changes of moduli with said modulation frequency.   
     
     
       12. Signal processing apparatus (410) as claimed in claim 11 in which said synchronizer means (276, 322) comprises a flip-flop (278, 280). 
     
     
       13. Signal processing apparatus (410) as claimed in claim 11 in which said apparatus further comprises: channelizing means, comprising means (244) for dividing a frequency in said feedback path (206) by a variable modulus, for channelizing a frequency in said feedback path; and   preventing means (246), being operatively connected to said modulation oscillator (256) and to said channelizing means, for preventing interference between said channelizing means and the second said phase-locking means (234, 256, 276, 322).   
     
     
       14. Signal processing apparatus (410) as claimed in claim 10 in which said apparatus includes means, comprising a dual modulus divider (234) that is interposed into said feedback path (206), and comprising a variable modulus divider (244) that is operatively connected to said dual modulus divider, for channelizing a frequency in said feedback path. 
     
     
       15. Signal processing apparatus (410) as claimed in claim 9 in which said apparatus comprises means (234, 244) for channelizing a frequency in said feedback path (206). 
     
     
       16. A method for processing electrical signals which includes receiving an angularly modulated signal that includes frequency deviations, producing a reduced-frequency signal from said angularly modulated signal, and producing a demodulated output of said reduced-frequency signal, in which said step of producing said reduced-frequency signal comprises: a) phase locking an output frequency of a smaller closed loop to a reference frequency;   b) low-pass filtering a forward path of said smaller closed loop;   c) forming a larger closed loop that includes said smaller closed loop;   d) deriving a signal from said larger closed loop;   e) modulating a feedback path of said smaller closed loop as a function of said derived signal;   f) phase locking said larger closed loop to said phase-locked output frequency; and   g) varying a frequency in said forward path as a function of said derived signal to obviate frequency response limitations imposed on said phase-locking steps by said low-pass filtering step.   
     
     
       17. A method as claimed in claim 16 in which said step of modulating said feedback path as a function or said derived signal comprises: a) generating a modulation frequency that is a function of said derived signal; and   b) modulating said feedback path as an exact mathematical function of said modulation frequency.   
     
     
       18. A method as claimed in claim 17 in which said modulating of said feedback path as an exact mathematical function of said modulation frequency comprises: a) changing a frequency in said feedback path; and   b) synchronizing said changing step with said modulation frequency.   
     
     
       19. A method as claimed it claim 17 in which said modulating of said feedback path as an exact mathematical function of said modulation frequency comprises: a) dividing a frequency in said feedback path by dual moduli; and   b) synchronizing changes in said moduli with said modulation frequency.   
     
     
       20. A method as claimed in claim 19 in which said method further comprises: a) maintaining said reference frequency substantially constant;   b) selectively dividing a frequency in said feedback path by variable moduli; and   c) preventing interference between said modulating and selective dividing steps.   
     
     
       21. A method as claimed in claim 17 in which said method further comprises: a) maintaining said reference frequency substantially constant;   b) channelizing a frequency in said feedback path; and   c) preventing interference between said modulating and said channelizing steps.   
     
     
       22. A method as claimed in claim 16 in which said method further comprises: a) maintaining said reference frequency substantially constant; and   b) channelizing said output frequency.   
     
     
       23. A method for producing a demodulated output of an angularly modulated signal that includes phase locking a larger closed loop that includes a smaller closed loop, in which said phase-locking step comprises: a) producing a phase-locked output frequency by phase locking forward and feedback paths of said smaller loop;   b) supplying said phase-locked output frequency to said larger closed loop;   c) deriving a signal from said larger closed loop;   d) varying a frequency in said feedback path as a function of said derived signal;   e) low-pass filtering said forward path of said smaller closed loop; and   f) varying a frequency in said forward path of said smaller closed loop as a function of said derived signal to obviate frequency response limitations imposed by said filtering step.   
     
     
       24. A method as claimed in claim 23 in which said step of varying a frequency in said feedback path comprises removing pulses from said feedback path. 
     
     
       25. An method as claimed in claim 23 in which said step of varying a frequency in said feedback path comprises adding pulses to said feedback path. 
     
     
       26. A method as claimed in claim 23 in which said step of varying a frequency in said feedback path comprises dividing a frequency in said feedback path by dual moduli. 
     
     
       27. A method as claimed in claim 23 in which said step of varying a frequency in said feedback path comprises mixing another frequency with said frequency in said feedback path. 
     
     
       28. A method as claimed in claim 23 in which said step of varying a frequency in said feedback path comprises: a) deriving a frequency from said derived signal;   b) developing quadrature frequencies from said derived frequency; and   c) mixing said quadrature frequencies with a frequency in said feedback path.   
     
     
       29. A method as claimed in claim 23 in which said step of varying a frequency in said feedback path comprises: a) deriving a frequency that is a function of said derived signal; and   b) preventing a change in signal level in said feedback path as a function of said derived frequency.   
     
     
       30. A method as claimed in claim 23 in which said step or of varying a frequency in said feedback path comprises: a) deriving a frequency that is a function of said derived signal; and   b) varying said frequency in said feedback path as an exact mathematical function of said derived frequency.   
     
     
       31. A method as claimed in claim 30 in which said step of varying a frequency in said feedback path as an exact mathematical function of said derived frequency comprises: a) selectively dividing a frequency in said feedback path by dual moduli; and   b) synchronizing changes in said moduli with said derived frequency.   
     
     
       32. A method as claimed in claim 31 in which said method further comprises: a) dividing said frequency in said feedback path by variable moduli;   b) controlling said variable moduli separate from said synchronizing step: and   c) preventing interference between the two recited dividing steps.   
     
     
       33. A method as claimed in claim 30 in which said method further comprises: a) channelizing a frequency in said feedback path; and   b) preventing interference between said varying and channelizing steps.   
     
     
       34. A method as claimed in claim 23 in which said method further comprises channelizing a frequency in said feedback path.