Assisting operating-system interrupts using application-based processing

Abstract

A microprocessor having registers is provided with a subset of instructions and is capable of operating in association with an operating system. The subset of instructions can be issued by an application running on the microprocessor for saving at least a portion of at least one of the plurality of registers not saved by the operating system during interrupt processing. Such an arrangement enables applications to be written for advanced microprocessors which have word lengths and register widths which exceed the word and register sizes for which the operating system was designed.

What I claim is: 
     
       1. A method for processing an interrupt on a computer, comprising the steps of: (a) running an application on the computer;   (b) receiving a call from outside the application to interrupt running of the application; and   (c) transferring interrupt-processing control to the application after receiving the call for the interrupt.   
     
     
       2. The method of claim 1, wherein the computer includes an operating system and step (c) further comprises the step of storing contents of at least one register, wherein the contents are not saved by the operating system during the interrupt and the contents are necessary for a graceful resumption of the application after the interrupt. 
     
     
       3. The method of claim 2, further comprising the steps of: (d) executing a deferred interrupt;   (e) restoring the contents of the at least one register; and   (f) resuming the application from a point of interruption.   
     
     
       4. The method of claim 3, wherein: step (a) further comprises the step of loading at least one of the plurality of registers with an address of a subroutine in the application;   step (d) comprises the steps of: (1) saving a state of the subroutine; and   (2) restoring the state of the subroutine;     steps (e) and (f) are executed by the restored subroutine; and   further comprising the step of deleting the address of the subroutine from the at least one of the plurality of registers.   
     
     
       5. The method of claim 1, wherein the computer is adapted to operate in an extended mode or a conventional mode and step (a) further comprises the step causing the computer to operate in the extended mode. 
     
     
       6. The method of claim 5, wherein the extended mode comprises at least one of 1) a register having a larger width than a register of the conventional mode and 2) a register not present in the conventional mode. 
     
     
       7. A computer-implemented method for switching between tasks being handled by an operating system and a processor, the processor having a conventional mode and an extended mode, the extended mode using registers and instructions of the conventional mode, comprising the steps of: (a) advising an application of an impending task switch by the operating system away from the application; and   (b) advising the application of an impending task switch by the operating system back to the application, wherein steps (a) and (b) occur independently of the operating system.   
     
     
       8. The method of claim 7, wherein step (a) further comprises the step of saving data associated with the extended mode. 
     
     
       9. The method of claim 8, wherein step (a) further comprises the step of delaying notification of the operating system by the processor of the impending task switch. 
     
     
       10. The method of claim 9, wherein the data saving and the delayed notification are enabled by the application. 
     
     
       11. The method of claim 8, wherein at least some of the data is in an extension of a conventional mode register associated with the extended mode. 
     
     
       12. The method of claim 8, wherein at least some of the data is in a register not present in the conventional mode. 
     
     
       13. The method of claim 7, wherein the operating system uses only the conventional mode. 
     
     
       14. The method of claim 7, wherein step (b) further comprises the step of delaying the task switch by the operating system until it is enabled by the application. 
     
     
       15. An application adapted to run on a processor having a plurality of registers, wherein an operating system running on the processor does not save all of the contents of all of registers of the processor during interrupts, wherein the application is adapted to issue a subset of instructions to the processor to ensure saving of all of the contents of all of the registers during each interrupt. 
     
     
       16. The invention of claim 15, wherein: the processor is operable in either a conventional mode or an extended mode; and   the subset of instructions comprises: (1) an instruction to cause operation of the processor in the extended mode;   (2) an instruction to allow execution of a deferred interrupt; and   (3) an instruction to resume the application from a point of interruption.     
     
     
       17. The invention of claim 16, wherein instruction (1) is adapted to load at least one of the plurality of registers with an address of a subroutine in the application, the subroutine being operable to control saving of the contents of the at least one register. 
     
     
       18. The invention of claim 17, wherein the subroutine is adapted to be called when the processor receives the interrupt. 
     
     
       19. The invention of claim 17, wherein: instruction (2) is adapted to be issued by the subroutine in the application;   the processor stores a state of the subroutine during the execution of the deferred interrupt;   the processor restores the state of the subroutine at termination of the execution of the deferred interrupt;   the restored subroutine is adapted to issue a command to the processor to restore the contents of the at least one register;   the subroutine is adapted to issue an instruction from the subset of instructions to the processor for causing the processor to resume execution of the application from a point of interruption; and   the address of the subroutine is deleted from the at least one of the plurality of registers when the application is unloaded from the processor.   
     
     
       20. The invention of claim 16, wherein the extended mode comprises at least one of 1) a register having a larger width than a register associated with operation in the conventional mode and 2) a register not present in the conventional mode.