US5729703AExpiredUtility

Bus control operating system having bi-directional address lines, integrated onto same chip as main controller

Assignee: SAMSUNG ELECTRONICS CO LTDPriority: Sep 20, 1991Filed: Apr 29, 1996Granted: Mar 17, 1998
Est. expirySep 20, 2011(expired)· nominal 20-yr term from priority
G06F 13/4217G06F 13/40
23
PatentIndex Score
10
Cited by
11
References
8
Claims

Abstract

A bus control operating system integrated in one chip with a main controller, which employs some of address bus lines operated in bi-directional mode, by interchanging signals between the main controller and the address source. As a result, if an external address source has to utilize address bus and data bus, an additional bus line for the external address source is not required and an additional external bus controller does not need to be manufactured.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A bus controller operating system comprising: a main controller;   a bus controller integrated on a single integrated circuit chip with said main controller;   an external address source;   an external target device;   a bi-directional address bus lines constructed and arranged to carry address signals from said bus controller to said external target device and external source address signals from said external address source to said bus controller;   an internal address bus connected between said main controller and said bus controller for carrying internal address signals; and   internal data bus lines connected between said main controller and said bus controller for carrying data signals; wherein said bus controller comprises: an input register for storing one of said external address signals and said internal address signals received from at least one address source through one of said external bi-directional address bus lines connected to said external address source and said internal address bus;   an address decoder for decoding address signals transmitted from said input register and transmitting a decoded signals to designate the target device;   a control signal buffer for transmitting a second internal control signal in correspondence with a first internal control signal generated by said main controller;   a bus interface controller constructed and arranged to transmit a characteristic control signal to said at least one address source in correspondence with said second control signal transmitted from said control signal buffer and said decoded signal from said address decoder;   a data controller constructed and arranged to transmit a fourth control signal in correspondence with said characteristic control signal received from said bus interface controller;   a data buffer constructed and arranged to receive said fourth control signal transmitted by said data controller and receiving and transmitting data through said internal data bus lines and external data bus lines; and   an address bus controller constructed and arranged to transmit said address signals to the target device through said bi-directional address bus line, after receiving a signal from said input register and said characteristic control signal transmitted from said bus interface controller.     
     
     
       2. A bus controller operating system comprising: a main controller;   a bus controller integrated on a single integrated circuit chip with said main controller;   an external address source;   an external target device;   bi-directional address bus lines constructed and arranged to carry address signals from said bus controller to said external target device whereby an external address bus controller is not needed and external source address signals from said external address source to said bus controller;   an internal address bus connected between said main controller and said bus controller for carrying internal address signals; and   internal data bus lines connected between said main controller and said bus controller for carrying data signals.   
     
     
       3. A bus controller operating system as claimed in claim 2, wherein said internal address bus is a uni-directional address bus. 
     
     
       4. A bus controller operating system as claimed in claim 3, wherein said internal data bus is a bi-directional address bus. 
     
     
       5. A bus controller operating system as claimed in claim 4, further including a bi-directional external data bus for carrying data signals bi-directionally between said external target device and said bus controller and bi-directionally between said external address source and said bus controller. 
     
     
       6. A bus controller operating system as claimed in claim 2, wherein said internal data bus is a bi-directional address bus. 
     
     
       7. A bus controller operating system as claimed in claim 6, further including a bi-directional external data bus for carrying data signals bi-directionally between said external target device and said bus controller and bi-directionally between said external address source and said bus controller. 
     
     
       8. A bus controller operating system as claimed in claim 2, further including a bi-directional external data bus for carrying data signals bi-directionally between said external target device and said bus controller and bi-directionally between said external address source and said bus controller.

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