Semiconductor memory device of which prescribed state of operation is terminated under a prescribed condition and method of operating a semiconductor memory device for terminating prescribed state of operation

Abstract

In the semiconductor memory device in accordance with the present invention, when test mode is entered at WCbR+super V IH +address key timing, the test mode is terminated only at the WCbR+super V IH +address key timing. Therefore, when refresh is to be started in the test mode, erroneous entrance to another test mode can be prevented, ensuring highly reliable testing. Further, since it is not necessary to take into account the special condition to enter the refreshing operation in the test mode, formation of a test pattern is facilitated.

What is claimed is: 
     
       1. A semiconductor memory device, comprising: a detecting means for receiving a plurality of first mode signals and a second mode signal, for outputting a detection signal when said second mode signal is at a prescribed potential higher than a power supply potential at a prescribed timing defined by a combination of the plurality of the first mode signals; and   a control signal generating means for receiving a third mode signal, for outputting a first control signal when said third mode signal attains to a first level and said detection signal is received, and for outputting a second control signal when said third mode signal attains to a second level and said detection signal is received; wherein   the semiconductor memory device enters a prescribed state of operation in response to said first control signal and goes out from said prescribed state of operation in response to said second control signal.   
     
     
       2. The semiconductor memory device according to claim 1, wherein one of said plurality of first mode signals is a row address strobe signal;   another of said plurality of first mode signals is a column address strobe signal;   still another of said plurality of first mode signals is a write enable signal;   said second mode signal is a signal input through any of a plurality of address pins; and   said third mode signal is a signal derived from at least one of said plurality of address pins other than that one through which said second mode signal is input.   
     
     
       3. The semiconductor memory device according to claim 2, wherein said prescribed timing is a timing at which said row address strobe signal attains to a third level after said column address strobe signal has attained to a fourth level and said write enable signal has attained to a fifth level.   
     
     
       4. The semiconductor memory device according to claim 3, wherein said prescribed state of operation is a test mode.   
     
     
       5. The semiconductor memory device according to claim 1, further comprising: another control signal generating means for receiving the plurality of first mode signals, for outputting a third control signal at the prescribed timing defined by the combination of the plurality of the first mode signals, and for outputting a fourth control signal at another prescribed timing defined by another combination of the plurality of the first mode signals; wherein the semiconductor memory device enters the other prescribed state of operation in response to said third control signal and goes out from said another prescribed state of operation in response to said fourth control signal.   
     
     
       6. The semiconductor memory device according to claim 5, wherein said other prescribed state of operation is a test mode.   
     
     
       7. The semiconductor memory device according to claim 5, wherein one of said plurality of first mode signals is a row address strobe signal;   another of said plurality of first mode signals is a column address strobe signals; and   still another of said plurality of first mode signals is a write enable signal.   
     
     
       8. The semiconductor memory device according to claim 7, wherein said prescribed timing is a timing at which said row address strobe signal attains to a third level after said column address strobe signal has attained to a fourth level and said write enable signal has attained to a fifth level, and   said other prescribed timing is a timing at which said row address strobe signal attains to a sixth level after having attained to a seventh level for a certain time period while said column address strobe signal is at an eighth level.   
     
     
       9. The semiconductor memory device according to claim 7, wherein said prescribed timing is a timing at which said row address strobe signal attains to a third level after said column address strobe signal has attained to a fourth level and said write enable signal has attained to a fifth level, and   said other prescribed timing is a timing at which said row address strobe attains to a ninth level after having attained to a tenth level following said column address strobe signal attaining to an eleventh level.   
     
     
       10. A method of operating a semiconductor memory device comprising the steps of: inputting a plurality of first mode signals such that levels of the signals change at a prescribed timing;   inputting a second mode signal at a prescribed potential higher than a power supply potential;   outputting a detection signal when said second mode signal at said prescribed potential is received while said plurality of first mode signals of which levels change at said prescribed timing are received;   inputting a third mode signal at a first level;   outputting a first control signal when said third mode signal at said first level is received and said detection signal is received;   entering a prescribed state of operation in response to said first control signal;   inputting said third mode signal at a second level;   outputting a second control signal when said third mode signal at said second level is received and said detection signal is received; and   going out from said prescribed state of operation in response to said second control signal.   
     
     
       11. The method of operating a semiconductor memory device according to claim 10, wherein one of said plurality of first mode signals is a row address strobe signal;   another of said plurality of first mode signals is a column address strobe signal;   still another of said plurality of first mode signals is a write enable signal;   said second mode signal is a signal input through any of a plurality of address pins; and   said third mode signal is a signal input through at least one of said plurality of address pins other than that one through which said second external signal is input.   
     
     
       12. The method of operating a semiconductor memory device according to claim 11, wherein said prescribed timing is a timing at which said row address strobe signal attains to a third level after said column address strobe signal has attained to a fourth level and said write enable signal has attained to a fifth level.   
     
     
       13. The method of operating a semiconductor memory device according to claim 12, wherein said prescribed state of operation is a test mode.   
     
     
       14. The method of operating a semiconductor memory device according to claim 5, further comprising the steps of: outputting a third control signal when said plurality of first mode signals of which levels change at said prescribed timing are received;   entering another prescribed state of operation in response to said third control signal;   outputting a fourth control signal when said plurality of first mode signals of which levels change at the other prescribed timing are received; and   going out from said other prescribed state of operation in response to said fourth control signal.   
     
     
       15. The method of operating a semiconductor memory device according to claim 14, wherein said other prescribed state of operation is a test mode.   
     
     
       16. The method of operating a semiconductor memory device according to claim 14, wherein one of said plurality of first mode signals is a row address strobe signal;   another of said plurality of first mode signals is a column address strobe signal; and   still another of said plurality of first mode signals is a write enable signal.   
     
     
       17. The method of operating a semiconductor memory device according to claim 16, wherein said prescribed timing is a timing at which said row address strobe signal attains to a third level after said column address strobe signal has attained to a fourth level and said write enable signal has attained to a fifth level, and   said other prescribed timing is a timing at which said row address strobe signal attains to a sixth level after having attained to a seventh level for a certain time period while said column address strobe signal is at an eighth level.   
     
     
       18. The method of operating a semiconductor memory device according to claim 16, wherein said prescribed timing is a timing at which said row address strobe signal attains to a third level after said column address strobe signal has attained to a fourth level and said write enable signal has attained to a fifth level, and   said other prescribed timing is a timing at which said row address strobe signal attains to a ninth level after having attained to a tenth level following said column address strobe signal attaining to an eleventh level.