Electrically programmable non-volatile semiconductor memory including series connected memory cells and decoder circuitry for applying a ground voltage to non-selected circuit units

Abstract

A semiconductor memory includes memory cells divided into a plurality of a series circuit units arranged in matrix fashion and comprising a plurality of memory cells connected in series. The memory cells each consist of a non-volatile transistor having a control gate electrode, a floating gate electrode and an erase gate electrode, and may comprise EEPROM cells. One end of each series circuit unit is coupled to a bit line with the circuit units in a given column of circuit units being coupled to the same bit line. Row lines are provided wherein each circuit unit in a given row of circuit units has the control gate electrodes of its memory cells coupled to a row line, the control gate electrodes of each memory cell in a given row of memory cells being connected to a common row line. A voltage by which a selected non-volatile transistor is driven to its saturation state is applied to the control gate electrode of the selected transistor through the corresponding row line. Another voltage is applied to the control gate electrodes of the remaining non-selected non-volatile transistors of the series circuit unit. A ground voltage, or zero volts, may be applied to the row, lines in certain non-selected circuit units.

I claim: 
     
       1. A semiconductor memory device, comprising: memory cells formed in a row and column array, wherein the memory cells in each column are arranged to form circuit units each including at least two memory cells connected in series;   a plurality of bit lines, each bit line connecting the circuit units in one column of said array;   a plurality of row lines, each row line connecting the memory cells in one row of said array;   decoding means responsive to address data for selecting a memory cell in one of said circuit units by applying voltages to said row lines and said bit lines, said decoding means including row decoding means responsive to the address data for applying a ground voltage to all row lines other than the row lines coupled to the memory cells in said one of said circuit units.   
     
     
       2. The semiconductor memory device according to claim 1, wherein said circuit units each comprise four memory cells connected in series. 
     
     
       3. The semiconductor memory device according to claim 1, wherein said memory cells comprise electrically programmable non-volatile transistors. 
     
     
       4. The semiconductor memory device according to claim 3, wherein said electrically programmable non-volatile transistors each include a control gate electrode, a floating gate electrode, and means for erasing data stored therein. 
     
     
       5. The semiconductor memory device according to claim 4, wherein said means for erasing data comprises means for electrically erasing data. 
     
     
       6. The semiconductor memory device according to claim 5, wherein said means for electrically erasing data comprises an erase gate electrode. 
     
     
       7. A semiconductor memory device, comprising: memory cells formed in a row and column array, wherein the memory cells in each column are arranged to form circuit units each including at least two memory cells connected in series;   a plurality of bit lines, each bit line connecting the circuit units in one column of said array;   a plurality of row lines, each row line connecting the memory cells in one row of said array;   decoding means responsive to address data for selecting a memory cell in one of said circuit units by applying voltages to said row lines and said bit lines, said decoding means including row decoding means responsive to the address data for applying a first voltage to the row line coupled to the selected cell of said one of said circuit units, a second voltage to the row lines coupled to unselected memory cells of said one of said circuit units, and a ground voltage to all other row lines.   
     
     
       8. The semiconductor memory device according to claim 7, wherein said circuit units each comprise four memory cells connected in series. 
     
     
       9. The semiconductor memory device according to claim 7, wherein said memory cells comprise electrically programmable non-volatile transistors. 
     
     
       10. The semiconductor memory device according to claim 9, wherein during a data reading operation, the first voltage is higher than a threshold voltage of a non-volatile transistor storing low-level binary data and lower than a threshold voltage of a non-volatile transistor storing high-level binary data, and the second voltage is higher than the threshold voltage of the non-volatile transistor storing the high-level binary data. 
     
     
       11. The semiconductor memory device according to claim 9, wherein during a data writing operation, the first voltage drives the non-volatile transistor of the selected memory cell of said one of said circuit units to a saturation state, and the second voltage drives the non-volatile transistors of the unselected memory cells in said one of said circuit units to a non-saturation state. 
     
     
       12. The semiconductor memory device according to claim 9, wherein said electrically programmable non-volatile transistors each include a control gate electrode, a floating gate electrode, and means for erasing data stored therein. 
     
     
       13. The semiconductor memory device according to claim 12, wherein said means for erasing data comprises means for electrically erasing data. 
     
     
       14. The semiconductor memory device according to claim 13, wherein said means for electrically erasing data comprises an erase gate electrode. 
     
     
       15. A semiconductor memory device, comprising: first and second circuit units, each of said first and second circuit units having a first end connected to a predetermined potential and comprising at least two memory cells connected in series;   a bit line connected to second ends of each of said first and second circuit units;   a plurality of row lines, each row line connected to one of the memory cells of said first and second circuit units;   decoding means responsive to address data for selecting a memory cell in one of said first and second circuit units by applying voltages to said row lines and said bit line, said decoding means including row decoding means responsive to the address data for applying a first voltage to the row line coupled to the selected cell of said one of said first and second circuit units, a second voltage to the row lines coupled to unselected memory cells of said one of said first and second circuit units, and a ground voltage to all row lines coupled to the memory cells in the other of said first and second circuit units.   
     
     
       16. The semiconductor memory device according to claim 15, wherein said circuit units each comprise four memory cells connected in series. 
     
     
       17. The semiconductor memory according to claim 16, wherein said row decoding means comprises: a first row decoder circuit coupled to the row lines connected to the memory cells of said first circuit unit; and   a second row decoder circuit coupled to the row lines connected to the memory cells of said second circuit unit.   
     
     
       18. The semiconductor memory device according to claim 15, wherein said memory cells comprise electrically programmable non-volatile transistors. 
     
     
       19. The semiconductor memory device according to claim 18, wherein during a data reading operation, the first voltage is higher than a threshold voltage of a non-volatile transistor storing low-level binary data and lower than a threshold voltage of a non-volatile transistor storing high-level binary data, and the second voltage is higher than the threshold voltage of the non-volatile transistor storing the high-level binary data. 
     
     
       20. The semiconductor memory device according to claim 18, wherein during a data writing operation, the first voltage drives the non-volatile transistor of the selected memory cell of in said one of said first and second circuit units to a saturation state, and the second voltage drives the non-volatile transistors of unselected memory cells in said one of said first and second circuit units to a non-saturation state. 
     
     
       21. The semiconductor memory device according to claim 18, wherein said electrically programmable non-volatile transistors each include a control gate electrode, a floating gate electrode, and means for erasing data stored therein. 
     
     
       22. The semiconductor memory device according to claim 21, wherein said means for erasing data comprises means for electrically erasing data. 
     
     
       23. The semiconductor memory device according to claim 22, wherein said means for electrically erasing data comprises an erase gate electrode. 
     
     
       24. A semiconductor memory device, comprising: first and second circuit units, each of said first and second circuit units having a first end connected to a predetermined potential and comprising at least two memory cells connected in series;   a bit line connected to second ends of each of said first and second circuit units;   a plurality of row lines, each row line connected to one of the memory cells of said first and second circuit units;   decoding means responsive to address data for selecting a memory cell in one of said first and second circuit units by applying voltages to said row lines and said bit line, said decoding means including row decoding means responsive to the address data for applying a first voltage to the row line coupled to the selected cell of said one of said first and second circuit units, a second voltage to the row lines coupled to unselected memory cells of said one of said first and second circuit units, and a ground voltage to all row lines coupled to the memory cell in the other of said first and second circuit units,   wherein said row decoding means comprises: a first row decoder circuit coupled to the row lines connected to the memory cells of said first circuit unit; and   a second row decoder circuit coupled to the row lines connected to the memory cells of said second circuit unit, and     wherein said address data comprises address data bits and each of said first and second row decoder circuits comprises: a row group decoder receiving first ones of said address data bits and outputting a row group decoder output signal;   row part decoders receiving second ones of said address data bits and outputting corresponding row part decoder output signals;   a row group decoder buffer receiving said row group decoder output signal and outputting a row group decoder buffer output signal; and   decoder output buffers, each connected to a corresponding one of said row lines and responsive to said row group decoder output signal, a corresponding one of said row part decoder output signals, and said row group decoder buffer output signal, for selectively outputting one of said first voltage, said second voltage, and said ground voltage to the corresponding row lines.     
     
     
       25. The semiconductor memory device according to claim 24, wherein said row group decoder comprises: input terminals receiving said first ones of said address data bits;   an output terminal for outputting said row group decoder output signal;   a plurality of first metal oxide semiconductor (MOS) transistors of a first conductivity type connected in series between said output terminal and a first potential, the gates of each of said first MOS transistors supplied with a respective one of said first ones of said address data bits; and   a plurality of second MOS transistors of a second conductivity type opposite the first conductivity type, each connected between said output terminal and a second potential, the gates of each of said second MOS transistors supplied with a respective one of said first ones of said address data bits.   
     
     
       26. The semiconductor memory device according to claim 24, wherein each row part decoder comprises: input terminals receiving said second ones of said address data bits;   an output terminal for outputting a corresponding one of said row part decoder output signals;   a plurality of first metal oxide semiconductor (MOS) transistors of a first conductivity type connected in series between said output terminal and a first potential, the gates of each of said first MOS transistors supplied with a respective one of said second ones of said address data bits; and   a plurality of second MOS transistors of a second conductivity type opposite the first conductivity type each connected between said output terminal and a second potential, the gates of each of said second MOS transistors supplied with a respective one of said second ones of said address data bits.   
     
     
       27. A semiconductor memory device, comprising: first and second circuit units, each of said first and second circuit units having a first end connected to a predetermined potential and comprising at least two memory cells connected in series;   a bit line connected to second ends of each of said first and second circuit units;   a plurality of row lines, each row line connected to one of the memory cells of said first and second circuit units;   decoding means responsive to address data for selecting a memory cell in one of said first and second circuit units by applying voltages to said row lines and said bit line, said decoding means including row decoding means responsive to the address data for applying a first voltage to the row line coupled to the selected cell of said one of said first and second circuit units, a second voltage to the row lines coupled to unselected memory cells of said one of said first and second circuit units, and a ground voltage to all row lines coupled to the memory cells in the other of said first and second circuit units,   wherein said row decoding means comprises: a first row decoder circuit coupled to the row lines connected to the memory cells of said first circuit unit; and   a second row decoder circuit coupled to the row lines connected to the memory cells of said second circuit unit,     wherein said address data comprises address data bits and each of said first and second row decoder circuits comprises: a row group decoder receiving first ones of said address data bits and outputting a row group decoder output signal:   row part decoders receiving second ones of said address data bits and outputting corresponding row part decoder output signals;   a row group decoder buffer receiving said row group decoder output signal and outputting a row group decoder buffer output signal; and   decoder output buffers, each connected to a corresponding one of said row lines and responsive to said row group decoder output signal, a corresponding one of said row part decoder output signals, and said row group decoder buffer output signal, for selectively outputting one of said first voltage, said second voltage, and said ground voltage to the corresponding row lines, and     wherein said row group decoder buffer comprises: a first input terminal receiving said row group decoder output signal;   a second input terminal receiving a clock signal;   an output terminal for outputting said row group decoder buffer output signal;   an inverter having an input connected to said first input terminal;   a first depletion-type metal oxide semiconductor (MOS) transistor of a first conductivity type having a first terminal connected to an output of said inverter, a second terminal connected to said output terminal, and a gate connected to a first potential;   a second MOS transistor of the first conductivity type having a first terminal connected to said output terminal, a second terminal, and a gate connected to said second terminal of said second MOS transistor;   a third MOS transistor of the first conductivity type having a first terminal connected to a second potential, a second terminal connected to the second terminal of said second MOS transistor, and a gate connected to said output terminal; and   a fourth MOS transistor of the first conductivity type having first and second terminals connected to said second input terminal and a gate connected to said second terminal of said second MOS transistor.     
     
     
       28. A semiconductor memory device, comprising: first and second circuit units, each of said first and second circuit units having a first end connected to a predetermined potential and comprising at least two memory cells connected in series;   a bit line connected to second ends of each of said first and second circuit units;   a plurality of row lines, each row line connected to one of the memory cells of said first and second circuit units;   decoding means responsive to address data for selecting a memory cell in one of said first and second circuit units by applying voltages to said row lines and said bit line, said decoding means including row decoding means responsive to the address data for applying a first voltage to the row line coupled to the selected cell of said one of said first and second circuit units, a second voltage to the row lines coupled to unselected memory cells of said one of said first and second circuit units, and a ground voltage to all row lines coupled to the memory cells in the other of said first and second circuit units,   wherein said row decoding means comprises: a first row decoder circuit coupled to the row lines connected to the memory cells of said first circuit unit; and   a second row decoder circuit coupled to the row lines connected to the memory cells of said second circuit unit,     wherein said address data comprises address data bits and each of said first and second row decoder circuits comprises: a row group decoder receiving first ones of said address data bits and outputting a row group decoder output signal;   row part decoders receiving second ones of said address data bits and outputting corresponding row part decoder output signals;   a row group decoder buffer receiving said row group decoder output signal and outputting a row group decoder buffer output signal; and   decoder output buffers, each connected to a corresponding one of said row lines and responsive to said row group decoder output signal, a corresponding one of said row part decoder output signals, and said row group decoder buffer output signal, for selectively outputting one of said first voltage, said second voltage, and said ground voltage to the corresponding row lines, and     wherein said decoder output buffers each comprise: a first input terminal for receiving a row part decoder output signal from a corresponding one of said row part decoders;   a second input terminal for receiving said row group decoder output signal;   a third input terminal for receiving said row group decoder buffer output signal;   a fourth input terminal receiving a clock signal;   a first inverter having an input connected to said first input terminal;   a depletion-type first metal oxide semiconductor (MOS) transistor of a first conductivity type having a first terminal connected to an output of said first inverter, a second terminal, and a gate connected to a first potential;   a second MOS transistor of the first conductivity type having a first terminal connected to the second terminal of said first MOS transistor, a second terminal, and a gate connected to said second terminal of said second MOS transistor;   a third MOS transistor of the first conductivity type having a first terminal connected to a second potential, a second terminal connected to said second terminal of said second MOS transistor, and a gate connected to said second terminal of said first MOS transistor;   a fourth MOS transistor of the first conductivity type having first and second terminals connected to said fourth input terminal, and a gate connected to said second terminal of said second MOS transistor;   a fifth MOS transistor of a second conductivity type, a sixth MOS transistor of the second conductivity type, a seventh MOS transistor of the first conductivity type and an eighth MOS transistor of the first conductivity type connected in series between said second potential and a third potential, a gate of said sixth MOS transistor connected to said second terminal of said first MOS transistor, a gate of said seventh MOS transistor connected to said second terminal of said first MOS transistor, and a gate of said eighth MOS transistor connected to said third input terminal;   a second inverter having an input connected to said third input terminal and an output connected to a gate of said fifth MOS transistor;   a ninth MOS transistor having a first terminal connected to a connection node between said sixth and seventh MOS transistors, a second terminal connected to a fourth potential, and a gate connected to said second input terminal; and   an output terminal connected to said connection node between said sixth and seventh MOS transistors.