Apparatus for varying the refresh rate for a DRAM in response to variation in operating voltages and method thereof

Abstract

A method and apparatus for operating a DRAM while varying the supply voltage provided thereto. A memory system is designed to attach to a DRAM. The DRAM is capable of maintaining data stored therein until supply voltage is varied beyond a predetermined voltage change level without the performance of a refresh operation. The system includes a power source coupled to the DRAM for providing supply voltage thereto and a refresh signal generator coupled to the DRAM for causing the DRAM to perform refresh operations wherein the charges associated with data bits stored within the DRAM memory cells are refreshed thereby maintaining the data integrity of data stored in the DRAM. The relative rates of supply voltage change and refresh signal provision are adjusted so as to ensure that refresh signals are provided to the DRAM prior to a point in time at which the change in supply voltage provided to the DRAM exceeds the predetermined voltage change level. Accordingly, it is possible to achieve reliable operation of the DRAM while the supply voltage provided thereto is varied.

Having described our invention, what we claim as new and desired to secure by Letters Patent is as follows: 
     
       1. In a memory system for supporting a memory capable of performing refresh operations to maintain a logical state for data stored therein, said memory system including a power source for providing supply voltage to the memory, and a refresh signal generator for providing a refresh signal to the memory for causing the memory to perform the refresh operation, and wherein a predetermined level of supply voltage variation may be tolerated by the memory prior to the performance of said refresh operations for said data, without loss of the logical state associated with the data stored therein, a method for operating the memory system to permit the supply voltage to be varied beyond said predetermined level of supply voltage variation without loss of the logical state associated with the data, the method comprising the steps of: A. sampling at a first one of said power source and said refresh signal generator, a first current rate of the other one of said power source and said refresh signal generator;   B. establishing a second current rate for said first one of said power source and said refresh signal generator, said established second current rate being derived from said sampled first current rate to ensure that the data stored in said memory has been refreshed before the supply voltage provided to the memory varies beyond said predetermined level;   C. adjusting said first one of said power source and said refresh signal generator to operate within said established second current rate; and   D. repeating steps A through C.   
     
     
       2. A method according to claim 1 wherein the first current rate is a current rate of supply voltage change from the power source sampled at said refresh signal generator, and the established second current rate is a current rate of refresh signal generation from the refresh signal generator. 
     
     
       3. A method according to claim 1 wherein the first current rate is a current rate of refresh signal generation from the refresh signal generator sampled at said power source, and the established second current rate is a current rate of supply voltage change from the power source. 
     
     
       4. A method according to claim 1 wherein the power source includes means for connecting to a plurality of power supplies. 
     
     
       5. A method according to claim 1 wherein said operation of said memory system to permit the supply voltage to be varied beyond said predetermined level of supply voltage variation includes powering up the memory system from a powered down state. 
     
     
       6. A method according to claim 1 wherein said operation of said memory system to permit the supply voltage to be varied beyond said predetermined level of supply voltage variation includes powering down the memory system from a powered up state. 
     
     
       7. A method according to claim 1 wherein the memory is a DRAM. 
     
     
       8. A method according to claim 7 wherein the DRAM has a self-refresh mode of operation. 
     
     
       9. A method according to claim 1 wherein the power source includes: a sampling logic element for sampling a current refresh rate of the refresh signal generator;   a conversion logic element responsive to said sampling logic element for converting the sampled current refresh rate into a current rate of supply voltage change from said power source; and   a signal generation means responsive to said conversion logic element for adjusting the rate of the supply voltage change from said power source to the converted current rate.   
     
     
       10. A method according to claim 1 wherein the power source includes: a clock circuit for receiving said refresh signal from said refresh signal generator and for generating clock pulses responsive to said received refresh signals;   an up/down counter coupled to said clock circuit for receiving said clock pulses, and a power up/down indication signal indicative of whether said memory system is to be powered up, or powered down, or is in a normal operation mode, said up/down counter counting up to a predetermined maximum count if said memory system is to be powered up and counting down to a predetermined minimum count when said memory system is to be powered down, said up/down counter generating a digital signal for each count upon receipt of any of said clock pulses;   a digital to analog converter coupled to said up/down counter for receiving said digital signals and for converting said received digital signals to corresponding analog signals; and   a voltage converter coupled to said digital to analog converter for receiving said analog signals and providing said supply voltage to said memory at a voltage level corresponding to the level of said received analog signals.   
     
     
       11. A method according to claim 1 wherein said refresh signal generator includes: a sampling logic element for sampling a current supply voltage change rate from said power source;   a conversion logic element responsive to said sampling logic element for converting the sampled current supply voltage change rate into a current rate of refresh signal generation from said refresh signal generator; and   a signal generation means responsive to said conversion logic element for adjusting the rate of the refresh signal generation from said refresh signal generator to the converted current rate.   
     
     
       12. A method according to claim 1 wherein said refresh signal generator includes: a sense circuit for receiving the supply voltage from the power source and providing an output signal having a frequency corresponding to the rate of change of the received supply voltage;   a counter for receiving said output signal and for providing a refresh rate signal having a frequency corresponding to a required refresh rate for said memory based upon the rate of change of the received supply voltage; and   a refresh generator for receiving said refresh rate signal and for generating said refresh signal for said memory at the rate of said received refresh rate signal.   
     
     
       13. A method according to claim 12 wherein said sense circuit further includes: a resistor and a capacitor coupled in series with one another for receiving said supply voltage from said power source and for providing an output voltage corresponding to the rate of change of the received supply voltage; and   a voltage controlled oscillator for receiving the output voltage from said coupled resistor and capacitor and for providing said output signal having a frequency corresponding to the received output voltage.   
     
     
       14. An apparatus for supporting a memory, said memory being capable of performing refresh operations to maintain a logical state for data stored therein, said memory further being capable of experiencing a predetermined level of supply voltage change prior to the performance of said refresh operations without loss of the logical state of the data stored therein, wherein said apparatus permits the supply voltage to be varied beyond said predetermined level without the loss of the logical state of the data stored in the memory, the apparatus comprising: a power source having means for coupling to said memory for providing supply voltage to the memory; and   a refresh signal generator having means for coupling to said memory for providing a refresh signal to said memory to cause said memory to perform said refresh operations and coupled to said power source to permit communication therebetween;   wherein the apparatus further includes means for iteratively sampling at a first one of said power source and said refresh signal generator, a first current rate of the other one of said power source and said refresh signal generator; and means for iteratively establishing a second current rate for said first one of said power source and said refresh signal generator, said iteratively established second current rate being derived from said iteratively sampled first current rate to ensure that the data stored in said memory has been refreshed before the supply voltage provided to the memory varies beyond said predetermined level; and means for iteratively adjusting said first one of said power source and said refresh signal generator to operate within said iteratively established second current rate.   
     
     
       15. An apparatus according to claim 14 wherein the iteratively sampled first current rate is a current rate of supply voltage change from the power source sampled at said refresh signal generator, and the iteratively established second current rate is a current rate of refresh signal generation from the refresh signal generator. 
     
     
       16. An apparatus according to claim 14 wherein the iteratively sampled first current rate is a current rate of refresh signal generation from the refresh signal generator sampled at said power source, and the iteratively established second current rate is a current rate of supply voltage change from the power source. 
     
     
       17. An apparatus according to claim 14 wherein the power source further includes means for connecting to a plurality of power supplies. 
     
     
       18. An apparatus according to claim 14 wherein an operation of said apparatus to permit the supply voltage to be varied beyond said predetermined level of supply voltage variation includes powering up the apparatus from a powered down state. 
     
     
       19. An apparatus according to claim 14 wherein an operation of said apparatus to permit the supply voltage to be varied beyond said predetermined level of supply voltage variation includes powering down the apparatus from a powered up state. 
     
     
       20. An apparatus according to claim 14 wherein the memory is a DRAM. 
     
     
       21. An apparatus according to claim 20 wherein the DRAM has a self-refresh mode of operation. 
     
     
       22. An apparatus according to claim 14 wherein the power source further includes: a sampling logic element for sampling a current refresh rate of the refresh signal generator;   a conversion logic element responsive to said sampling logic element for converting the sampled current refresh rate into a current rate of supply voltage change from said power source; and   a signal generation means responsive to said conversion logic element for adjusting the rate of the supply voltage change from said power source to the converted current rate.   
     
     
       23. An apparatus according to claim 14 wherein the power source further includes: a clock circuit for receiving said refresh signal from said refresh signal generator and for generating clock pulses responsive to said received refresh signals;   an up/down counter coupled to said clock circuit for receiving said clock pulses, and a power up/down indication signal indicative of whether said apparatus is to be powered up, or powered down, or is in a normal operation mode, said up/down counter counting up to a predetermined maximum count if said apparatus is to be powered up and counting down to a predetermined minimum count when said apparatus is to be powered down, said up/down counter generating a digital signal for each count upon receipt of any of said clock pulses;   a digital to analog converter coupled to said up/down counter for receiving said digital signals and for converting said received digital signals to corresponding analog signals; and   a voltage converter coupled to said digital to analog converter for receiving said analog signals and providing said supply voltage to said memory at a voltage level corresponding to the level of said received analog signals.   
     
     
       24. An apparatus according to claim 14 wherein said refresh signal generator further includes: a sampling logic element for sampling a current supply voltage change rate from said power source;   a conversion logic element responsive to said sampling logic element for converting the sampled current supply voltage change rate into a current rate of refresh signal generation from said refresh signal generator; and   a signal generation means responsive to said conversion logic element for adjusting the rate of the refresh signal generation from said refresh signal generator to the converted current rate.   
     
     
       25. An apparatus according to claim 14 wherein said refresh signal generator further includes: a sense circuit for receiving the supply voltage from the power source and providing an output signal having a frequency corresponding to the rate of change of the received supply voltage;   a counter for receiving said output signal and for providing a refresh rate signal having a frequency corresponding to a required refresh rate for said memory based upon the rate of change of the received supply voltage; and   a refresh generator for receiving said refresh rate signal and for generating said refresh signal for said memory at the rate of said received refresh rate signal.   
     
     
       26. An apparatus according to claim 25 wherein said sense circuit further includes: a resistor and a capacitor coupled in series with one another for receiving said supply voltage from said power source and for providing an output voltage corresponding to the rate of change of the received supply voltage; and   a voltage controlled oscillator for receiving the output voltage from said coupled resistor and capacitor and for providing said output signal having a frequency corresponding to the received output voltage.