US5703875AExpiredUtility

Integrated control and data message network

Assignee: HUGHES AIRCRAFT COPriority: Apr 10, 1996Filed: Apr 10, 1996Granted: Dec 30, 1997
Est. expiryApr 10, 2016(expired)· nominal 20-yr term from priority
Inventors:Robert Burnett
H04L 49/3018H04L 49/101H04Q 2213/1325H04L 49/254H04Q 2213/13174H04Q 2213/13213H04Q 11/04H04Q 2213/13103H04L 49/205H04Q 2213/1302H04Q 2213/13178H04Q 2213/13176H04Q 2213/1304
60
PatentIndex Score
49
Cited by
3
References
4
Claims

Abstract

A switch for communicating short control messages and longer data messages. The control and data switch comprises separate resources for control messages and for data messages, while sharing communication links. Each input port of the switch has a separate control message input FIFO buffer and a data message input FIFO buffer. These buffers allow a control message to preempt a data message that is currently in progress over a link. If there are control message words waiting to be transmitted over the link, they are given prior over any data message words that are ready for transmission over the same link. Preemption of an ongoing data message by a control message takes place without disrupting the data message, other than delaying it.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A switch for communicating control messages and data messages, said switch comprising: a plurality of input ports;   a plurality of control message first-in, first-out buffers, each of which is coupled to a selected one of the input ports;   a plurality of data message first-in, first-out buffers, each of which is coupled to a selected one of the input ports;   a plurality of multiplexers, each of which is coupled to a selected one of the control message buffers and a selected one of the data message buffers;   a core crossbar switch coupled to the plurality of multiplexers; and   a plurality of output ports coupled to the core crossbar switch.   
     
     
       2. The switch of claim 1 further comprising an additional first-in, first-out buffer coupled between a respective input port and a respective multiplexer. 
     
     
       3. The switch of claim 1 further comprising an input register coupled between a respective input port and the first-in, first-out buffers. 
     
     
       4. The switch of claim 1 further comprising a register for storing crossbar states for output ports of the core crossbar.

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