Method and apparatus for operating a microcomputer in an emulation mode to access an external peripheral

Abstract

Disclosed is a microcomputer capable of working in emulation mode with internal and external peripherals. The microcomputer comprises a central processing unit, an internal address decoder, an internal memory and internal peripherals connected to a data and address bus. The central processing unit has input/output ports for external access in user mode according to the invention. The input/output ports are connected to the external peripherals and to an external address decoder. The external address decoder sends out a signal applied to the central processing unit to block the pre-loading of the internal address decoder when an external peripheral is selected in emulation mode.

What is claimed is: 
     
       1. A microcomputer working in an emulation mode with at least one external peripheral to emulate another computer system capable of performing at least one function of the external peripheral, the microcomputer comprising: a central processing unit that outputs addresses of peripherals to be accessed,   at least one internal peripheral,   an internal address decoder that is pre-loaded with addresses in response to a system clock signal, the internal address decoder decoding each pre-loaded address and selecting a corresponding internal peripheral, and   an internal memory connected to the central processing unit by a data and address bus,   the central processing unit having first and second input/output ports that, in the emulation mode, are respectively connected to said at least one external peripheral and to an external address decoder, the external address decoder sending out a signal applied to the central processing unit when an external peripheral is selected by an address output from the central processing unit, said microcomputer being configured to block the pre-loading of the internal address decoder in response to the signal from the external address decoder.   
     
     
       2. A microcomputer according to claim 1, wherein an external memory is also connected to the first input/output port. 
     
     
       3. A microcomputer as recited in claim 1, wherein said central processing unit comprises at least one interrupt input, wherein interrupt request signals coming from the internal and external peripherals are applied respectively to the inputs of an OR gate, the output of which is connected to said at least one interrupt input, the interrupt request signal coming from an external peripheral being first applied to a first input of an AND gate, a second input of the AND gate receiving a signal indicating a mode of operation of the microcomputer. 
     
     
       4. A microcomputer as recited in claim 2, wherein said central processing unit comprises at least one interrupt input, wherein interrupt request signals coming from the internal and external peripherals are applied respectively to the inputs of an OR gate, the output of which is connected to said at least one interrupt input, the interrupt request signal coming from an external peripheral being first applied to a first input of an AND gate, a second input of the AND gate receiving a signal indicating a mode of operation of the microcomputer. 
     
     
       5. The microcomputer as recited in claim 1, wherein said central processing unit comprises at least one interrupt input responsive to interrupt request signals, generated by either the internal or external peripherals, an external interrupt only being accepted when the microcomputer is operating in the emulation mode. 
     
     
       6. A method for enabling a first microcomputer to emulate the performance of a second microcomputer, the second microcomputer capable of performing a specified circuit function that includes the manipulation of data in a required manner, the first microcomputer including at least one internal peripheral, the first microcomputer being unable to manipulate data in the manner required by the specified circuit function, the first microcomputer further including a processor, connected to the internal peripheral through an internal address bus and an internal data bus to communicate with the internal peripheral, an internal address decoder coupled to the internal address bus, and at least one input/output port, the method including the steps of: providing an external peripheral capable of manipulating data in the manner required by the specified circuit function;   providing an external address decoder to decode address signals;   coupling the external peripheral and the external address decoder through the at least one input/output port to the internal address and internal data buses to create a system address bus and a system data bus; and   operating the first microcomputer such that the processor communicates with the external peripheral over the system address bus and the system data bus to perform the specified circuit function, the step of operating including steps of: placing a plurality of address signals on the system address bus from the processor via the internal address bus:   decoding the address signals in the external address decoder;   pre-loading the internal address decoder with addresses on the internal address bus; and   sending a blocking signal from the external address decoder to the internal address decoder when an external address is detected on the system address bus by the external address decoder to block the pre-loading of the internal address decoder.     
     
     
       7. A method for enabling a first microcomputer to emulate the performance of a second microcomputer as recited in claim 6, wherein the first microcomputer includes internal address and data buses coupling the processor to the at least one internal peripheral, and wherein the method further includes the step of: coupling the at least one input/output port to the internal address and data buses.   
     
     
       8. A method for operating a microcomputer system, the system including a microcomputer having at least one internal peripheral and a processor, the microcomputer further including internal address and data buses coupling the processor to the at least one internal peripheral and an internal address decoder coupled to the internal address bus, the microcomputer having at least one input/output port, the system further including at least one external peripheral and an external address decoder that are external to the microcomputer, the method including the steps of: A. coupling the at least one input/output port to the internal address and data buses;   B. coupling the external peripheral and the external address decoder, through the at least one input/output port, to the internal address and data buses to create system address and data buses; and   C. operating the microcomputer to pass, via the processor the internal buses and the system buses, addresses and data between the processor the at least one internal peripheral and the at least one external peripheral, the at least one external peripheral being accessed by the processor over the system address and data buses, the step of operating including steps of: placing a plurality of address signals on the system address bus from the processor and decoding the address signals in the external address decoder;   pre-loading the internal address decoder with addresses on the internal address bus; and   sending a blocking signal from the external address decoder to the internal address decoder when an external address is detected on the system address bus by the external address decoder to block the pre-loading of the internal address decoder.     
     
     
       9. A method for operating a microcomputer system as recited in claim 8 wherein step C includes the steps of: specifying user and emulation modes for the microcomputer; and   inhibiting the at least one external peripheral so that it cannot interrupt the processor when the user mode is specified.   
     
     
       10. A microcomputer system, comprising: a microcomputer including; at least one internal peripheral;   a processor;   an internal address bus coupling the processor to the at least one internal peripheral;   an internal data bus coupling the processor to the at least one internal peripheral;   an internal address decoder, coupled to the internal address bus, that is pre-loaded with addresses on the intemal address bus; and   at least one input/output port coupled to the internal address and data buses;   an external address bus;   an external data bus;     at least one external peripheral that is external to the microcomputer, the at least one external peripheral being coupled, through the external address and data buses and the at least one input/output port, to the internal address and data buses so that the external peripheral can be accessed by the processor; and   an external address decoder external to the microcomputer and coupled to the external address and data buses, wherein the external address decoder decodes addresses placed on the external address bus, the external address decoder being adapted to send a blocking signal to block the preloading of the internal address decoder when an external address is detected on the external address bus by the external address decoder.   
     
     
       11. A microcomputer system as recited in claim 10, further comprising: at least one external memory, associated with the at least one external peripheral, coupled to the external address and data buses.   
     
     
       12. A microcomputer system as recited in claim 10, wherein the processor includes at least one interrupt input that is responsive to an external interrupt signal sourced by the at least one external peripheral. 
     
     
       13. A microcomputer system as recited in claim 12, wherein the microcomputer generates a mode output indicating whether the system is operating in user mode or in emulation mode, and wherein the system further includes means, responsive to the mode output, for inhibiting the external interrupt signal when the system is in user mode. 
     
     
       14. A microcomputer system as recited in claim 12, wherein the microcomputer generates a mode output indicating whether the system is operating in user mode or in emulation mode, and wherein the system further includes an inhibiting circuit that inhibits the external interrupt signal when the system is in user mode. 
     
     
       15. A microcomputer system as recited in claim 14, wherein the inhibiting circuit includes an AND gate that has a first input responsive to the external interrupt signal, and a second input responsive to the mode signal. 
     
     
       16. A microcomputer system, comprising: a microcomputer including; at least one intemal peripheral;   a processor;   an internal address bus coupling the processor to the at least one internal peripheral;   an internal data bus coupling the processor to the at least one internal peripheral;   an internal address decoder, coupled to the internal address bus, that is pre-loaded with addresses on the internal address bus: and   at least one input/output port coupled to the internal address and data buses;   an external address bus;   an external data bus;     first and second external peripherals that are external to the microcomputer and perform functions, the function performed by the first external peripheral being different from that performed by the second peripheral, the first and second external peripherals being coupled to the processor through the external address and data buses and the at least one input/output port so that the first and second external peripherals can be accessed by the processor; and   an external address decoder external to the microcomputer and coupled to the external address and data buses, wherein the external address decoder decodes addresses placed on the external address bus, the external address decoder being adapted to send a blocking signal to block the preloading of the intemal address decoder when an external address is detected by the external address decoder.   
     
     
       17. The microcomputer system recited in claim 16, further comprising a plurality of external memories, each respectively corresponding to one of the plurality of external peripherals. 
     
     
       18. A method for operating a first microcomputer in an emulation mode wherein the first microcomputer emulates the performance of a second microcomputer having an internal peripheral that performs a specified function, the first microcomputer having a processor, at least one internal peripheral, an internal address bus, an internal address decoder, and an internal data bus, the internal address and data buses coupling the processor to the at least one internal peripheral, the first microcomputer further having at least one input/output port coupled to the internal address and data buses, the method including the steps of: A. providing at least one external peripheral that performs the specified function;   B. providing an external address decoder;   C. coupling the external peripheral and the external address decoder, via the at least one input/output port, to the internal address and data buses; and   D. operating the first microcomputer so that the processor accesses the at least one external peripheral via the input/output port to perform the specified function, whereby the first microcomputer emulates the performance of the second microcomputer, the step of operating including steps of: placing a plurality of address signals on the internal address bus from the processor and decoding the address signals in the external address decoder;   pre-loading the internal address decoder with addresses on the internal address bus; and   sending a blocking signal from the external address decoder to the internal address decoder when an external address is detected by the external address decoder to block the pre-loading of the internal address decoder.     
     
     
       19. The method for operating a first microcomputer system in an emulation mode, as recited in claim 18, further comprising the steps of: E. providing an interrupt input in the processor that is responsive to an interrupt signal generated by either of the at least one intemal peripheral and the at least one external peripheral; and   F. enabling the interrupt signal from the external peripheral to be effective only when the first microcomputer is operating in an emulation mode.