Semiconductor memory device including sense amplifier for high-speed write operation

Abstract

A semiconductor memory device includes a memory cell array with each cell being connected to respective pairs of complementary bit lines, and a write circuit for writing data to the memory cells by applying complementary write signals to the complementary bit lines. The write circuit includes complementary data lines, a buffer circuit for applying complementary data signals to the data lines in response to the input data, and sense amplifier connected to the data lines and the bit lines for amplifying the data lines differential signals and for producing the complementary write signals.

What is claimed is: 
     
       1. A semiconductor memory device comprising: a memory cells section;   an input portion for receiving input data to be stored in said memory cells section;   a buffer means connected to said input portion and having a first output and a second output, said buffer means, in response to the input data, producing high level electrical potential at one of the first output and said second output and complementarily producing low level electrical potential at the other of said second output or said first output;   said memory cells section including a sense amplifier having a first input and a second input for receiving, respectively, an input electrical potential from said first output of said buffer means and an input electrical potential from said second output of said buffer means, said sense amplifier comparing said two input electrical potentials; said sense amplifier further having a first output and a second output which are respectively connected to corresponding bit line pairs connected to said memory cells section; said sense amplifier, in response to the result of comparison of said two input electrical potentials, producing high level electrical potential at one of said first output and said second output of said sense amplifier and complementarily producing a low level electrical potential at the other of said second output and said first output of said sense amplifier in order to store said input data in said memory cells section;   a first line for connecting said first output of said buffer means to said first input of said sense amplifier; and   a second line for connecting said second output of said buffer means to said second input of said sense amplifier,   wherein said device farther comprising: detection means for detecting a transitional change in level of said input data and producing a detection signal at an output of said detection means in response to said transitional change in level of said input data; and   switch means connected to said detection means for electrically connecting said first line to said second line for a short period in response to said detection signal, thereby pre-charging said first and second lines to be at substantially the same electrical potential level.   
     
     
       2. A semiconductor memory device comprising: a memory cell array with each cell being connected to respective pairs of complementary bit lines;   said memory cell array including write means for writing input data to said memory cells by applying complementary write signals to said complementary bit lines; and   means for equalizing said data lines prior to a write operation,   said write means comprising complementary data lines, buffer means for applying complementary data signals to said date lines in response to said input data, and amplifier means connected to said data lines and said bit lines for amplifying complementary data signals on said data lines to produce said complementary write signals,   wherein said equalizing means comprises a parallel transistor pair connected between said data lines, said parallel transistor pair connecting said data lines in response to a control signal active prior to a write operation, and   wherein said control signal pulses active in response to an input data transition and returns to inactive prior to a write operation.   
     
     
       3. The memory device of claim 2 wherein said amplifier means comprises a sense amplifier. 
     
     
       4. The memory device of claim 3 wherein said sense amplifier comprises a first pair of transistors each having an output and each having a gate connected to a respective one of said data lines, and a second pair of transistors with each second transistor having an output connected to a respective bit line, each transistor of said second transistor pair being in a cross-coupled configuration such that a gate is connected to one output of said first transistor pair and a corresponding drain is connected to the other output of said first transistor pair. 
     
     
       5. The memory device of claim 4 wherein each gate of said second transistor pair is connected to an output of one of said first pair of transistors associated with a data line that is complementary to said second transistor associated bit line. 
     
     
       6. The memory device according to claim 2 wherein said buffer means comprises a pair of buffer circuits, each of said buffer circuits having an output respectively connected to one of said data lines; each of said buffers having an input connected to input data signals and another input connected to complementary input data signals. 
     
     
       7. The memory device according to claim 6 wherein each of said buffer means comprises a pair of MOSFETS connected in series between a supply voltage and a reference whereby each of said buffer means produces a logic high signal that is at least a threshold voltage less than said supply voltage. 
     
     
       8. The memory device according to claim 2 wherein when said buffer means applies a logic high signal to said data lines, said logic high signal has a voltage level that is less than a supply voltage for the device. 
     
     
       9. The memory device according to claim 8 wherein said buffer means logic high voltage level is approximately V cc  -V th  -α. 
     
     
       10. The memory device of claim 2 wherein said equalizing means causes a substantially equal voltage potential to precharge said data lines, said voltage potential being approximately one-half the supply voltage. 
     
     
       11. The memory device of claim 2 wherein said equalizing means is active only prior to write operations that follow input data transitions.