Method and apparatus for writing and erasing flash memory

Abstract

A DRAM-compatible nonvolatile memory includes a FLASH memory and a logic controller. The logical controller accepts conventional DRAM command protocol and accepts data and addresses from DRAM data and address buses, respectively. The logic controller responds to repeated CAS-before-RAS signals and a write enable signal to initiate block erases and writes to the FLASH memory. The nonvolatile, DRAM-compatible memory is incorporated in a package having the same pin structure as a conventional DRAM package, such that the nonvolatile, DRAM-compatible memory can be mounted in a DRAM mount, such as a socket. Because the nonvolatile, DRAM-compatible memory can share common data, address, and command lines with conventional DRAMs, a single memory card can be produced containing both conventional DRAMs and the nonvolatile, DRAM-compatible memories.

I claim: 
     
       1. An integrated memory circuit, comprising: a single integrated circuit package having an external RAS input terminal and an external CAS input terminal;   an electrically erasable nonvolatile memory array within an integrated circuit package;   an address bus;   an address buffer within the integrated circuit package coupled to the address bus to receive addresses from the address bus, the address buffer having an address output connected to the electrically erasable nonvolatile memory array;   a row address line coupled to the memory array;   a row address select line coupled to the RAS input terminal and configured to receive a RAS signal according to volatile memory timing and logic states;   a column address line coupled to the electrically erasable nonvolatile memory array;   a column address select line coupled to the CAS input terminal and configured to receive a CAS signal according to volatile memory timing and logic states;   a logic controller within the integrated circuit package, the logic controller having a first input connected to the row address select line and a second input connected to the column address select line, the logic controller having a first output coupled to the electrically erasable nonvolatile memory, the logic controller being operative to supply commands according to electrically erasable nonvolatile memory timing and logic states in response to the RAS and CAS signals on the row address select line and column address select line; and   a block erase circuit within the integrated circuit package and coupled to receive commands from the logic controller, the block erase circuit further being coupled to the electrically erasable nonvolatile memory array, the block erase circuit being operative to provide commands to the electrically erasable nonvolatile memory array in response to commands from the logic controller.   
     
     
       2. The integrated memory circuit of claim 1 wherein the logic controller includes: a write enable input terminal; and   a write enable line coupled to the write enable input terminal from external to the integrated circuit package.   
     
     
       3. The integrated memory circuit of claim 1, further including a data input buffer within the integrated circuit package and having a data output connected to the nonvolatile memory array, the data input buffer further including a control input terminal, wherein the logic controller is coupled to the control input terminal to provide a store control signal to the control input terminal to store data from the data input buffer into the nonvolatile memory array. 
     
     
       4. The integrated memory circuit of claim 3, further including a data output buffer within the integrated circuit package and having a data input connected to the nonvolatile memory array, the data output buffer further including a control input terminal wherein the logic controller is connected to the control input terminal of the data output buffer to provide a read control signal to the control input terminal to read data from nonvolatile memory array into the data output buffer. 
     
     
       5. A reconfigurable memory board having nonvolatile memory capability comprising: a memory card having a data line input transfer line, a RAS line, a CAS line, and a plurality of chip mounts, each chip mount having a data input terminal coupled to the data input line, a data output terminal coupled to the data output line, a RAS input terminal coupled to the RAS line and a CAS input terminal coupled to the CAS line wherein the terminal patterns of the chip mounts are the same;   a plurality of volatile memory chips mountable in the chip mounts, each volatile memory chip having a RAS pin, a CAS pin, a data input pin, and a data output pin, respectively positioned in pin locations corresponding to the RAS input terminal, CAS input terminal, data input terminal and data output terminal, respectively; and   a plurality of nonvolatile memory chips mountable in the chip mounts, each nonvolatile memory chip having a RAS pin, a CAS pin, a data input pin, and a data output pin, respectively positioned in the pin locations corresponding to the RAS input terminal, CAS input terminal, data input terminal and data output terminal.   
     
     
       6. The reconfigurable memory circuit of claim 5 wherein the memory card includes a write enable line, and each of the volatile memory chips and the nonvolatile memory chips includes a write enable pin connectable to the write enable line wherein the write enable pins of the volatile memory chips and the nonvolatile memory chips have identical pin locations. 
     
     
       7. The reconfigurable memory board of claim 5 wherein each of the nonvolatile memory chips includes within the chip: a memory array; and   a logic controller connected to the RAS input terminal and the CAS input terminal, the logic controller further being coupled to the memory array to control data flow into and out of the memory array in response to signals on the RAS input terminal and the CAS input terminal.   
     
     
       8. The reconfigurable memory circuit of claim 7 wherein the nonvolatile memory chips comprise FLASH memory chips. 
     
     
       9. The reconfigurable memory circuit of claim 7 wherein the memory card is a single in-line memory module. 
     
     
       10. A memory card comprising: an address bus;   a row address line;   a column address line;   a row address select line;   a column address select line;   a data bus;   an integrated electrically erasable programmable read only memory circuit having a RAS input coupled to the row address select line and a CAS input coupled to the column address select line, a row address input coupled to the row address line, a column address input coupled to the column address line, an enable line, the electrically erasable programmable read only memory having an output coupled to the data bus; and   an integrated dynamic random access memory (DRAM) having a RAS input connected to the row address select line, a CAS input connected to the column address select line, a row address input coupled to the row address line and a column address input coupled to the column address line, the DRAM having an output coupled to the data bus.   
     
     
       11. The memory card of claim 10 wherein the integrated electrically erasable programmable read only memory circuit further includes a logic controller coupled to the RAS input. 
     
     
       12. The memory card of claim 11 wherein the logic controller is also coupled to the CAS input. 
     
     
       13. The memory card of claim 10 wherein the integrated electrically erasable programmable read only memory circuit further includes a data input buffer having a data input coupled to the data bus. 
     
     
       14. The memory card of claim 10, further including a write enable line and wherein the integrated electrically erasable programmable read only memory circuit includes a write enable input terminal coupled to the write enable line. 
     
     
       15. A method for storing data in a memory location in an electrically erasable programmable read only memory coupled to a logic controller, the memory location having an address, comprising: providing the address at an address bus;   storing the address in an address buffer coupled to receive addresses from the address bus;   providing a control sequence to the logic controller according to conventional DRAM command sequence timing and logic states;   generating an internal erase command with the logic controller in response to the control sequence;   supplying the internal erase command to the electrically erasable programmable read only memory;   supplying the address of the memory location from the address buffer to the electrically erasable programmable read only memory;   erasing the memory location in response to the internal erase command; and   writing data to the erased memory location.   
     
     
       16. The method of claim 15 wherein the step of providing a control sequence to the logic controller according to conventional DRAM command sequence timing and logic states comprises the steps of: providing a column address select signal to a column address select input of the logic controller;   providing a row address select signal to a row address select input of the logic controller; and   repeating the step of providing a column address select signal to the column address select input of the logic controller.   
     
     
       17. The method of claim 16 wherein the step of providing a control sequence to the logic controller further includes the step of: after repeating the step of providing the column address select signal to the column address selected input of the logic controller, repeating the step of providing the row address select signal to the row address select input of the logic controller.   
     
     
       18. The method of claim 17 wherein the step of providing a control sequence to the logical controller further includes the steps of: providing a write signal in a first state when performing the step of providing the column address select signal to the column address select input; and   providing the write signal in a second state when performing the step of repeating the step of providing the column address signal to the column address select input.   
     
     
       19. The method of claim 16, further including the step of storing data in a data buffer and wherein the step of writing data to the memory location comprises the steps of retrieving data from the data buffer and storing the retrieved data in the erased memory location. 
     
     
       20. A method for erasing data from a memory location in an electrically erasable nonvolatile memory coupled to a logic controller, the memory location having an address, comprising: providing the address to the electrically erasable nonvolatile memory;   providing a control sequence to the logic controller according to conventional DRAM command sequence timing and logic states;   generating an internal erase command with the logic controller in response to the control sequence;   supplying the internal erase command to the electrically erasable programmable read only memory;   entering an internal erase mode in the electrically erasable programmable read only memory in response to the internal erase command; and   erasing the memory location.   
     
     
       21. The method of claim 20, further including the step of: prewriting the memory location prior to erasing the memory location.   
     
     
       22. The method of claim 21 wherein the step of providing a control sequence to the logic controller according to conventional DRAM command sequence timing and logic states comprises the steps of: providing a column address select signal to a column address select input of the logic controller;   providing a row address select signal to a row address select input of the logic controller; and   repeating the step of providing a column address select signal to the column address select input of the logic controller.   
     
     
       23. The method of claim 22 wherein the step of providing a control sequence to the logic controller further includes the step of: after repeating the step of providing the column address select signal to the column address selected input of the logic controller, repeating the step of providing the row address select signal to the row address select input of the logic controller.   
     
     
       24. The method of claim 23 wherein the step of providing a control sequence to the logical controller further includes the steps of: providing a write enable signal in a first state when performing the step of providing the column address select signal to the column address select input; and   providing the write enable signal in a second state when performing the step of repeating the step of providing the column address signal to the column address select input.   
     
     
       25. The method of claim 22, further including the step of storing data in a data buffer and wherein the step of writing data to the memory location comprises the steps of retrieving data from the data buffer and storing the retrieved data in the erased memory location.