Video display control system having block write with opaque pattern control expansion

Abstract

A video random access memory is disclosed that performs a block write function for an opaque pattern color expansion. The video RAM, or VRAM, uses an input buffer for receiving and holding video input information. A first color register is coupled to the input buffer and holds a first color value. A second color register coupled to the input buffer is used to hold a second color value. A gate multiplexor couples to both first color register and the second color register with a color selection register being used to gate which color value from the first color register or the second color register should be asserted. A write control logic selects which color values are to be displayed. A third or mask register is coupled to the input buffer and the write control logic such that, based upon data from the input buffer, the mask register selects which pixel location is to be changed based on the color value selected by the color selection register as received from the write control logic.

I claim: 
     
       1. A video random access memory (VRAM) comprising: an input buffer for receiving and holding video input information;   a first color register, coupled to said input buffer, for holding a first color value from said input buffer;   a second color register, coupled to said input buffer, for holding a second color value from said input buffer;   a gate multiplexor, coupled to said first color register and said second color register;   a color selection register, coupled to said input buffer and to said gate multiplexor, that uses a color selection information signal from said input buffer for gating which color value from said first color register or said second color register should be asserted;   a write control logic, coupled to said gate multiplexor, for writing said selected color value and;   a mask register containing a plurality of bits, coupled to said input buffer and to said write control logic, that, based upon data from said input buffer which determine a state of each of said plurality of bits, selects which pixel location from among a plurality of pixel locations corresponding to each of said plurality of bits shall be changed based on the color value selected by said color selection register as output by said write control logic.   
     
     
       2. The VRAM according to claim 1 wherein said register are 8-bit registers. 
     
     
       3. The VRAM according to claim 1 further comprising a second multiplexor coupled to said gate multiplexor, said input buffer, and to said write control logic for gating data either from said first and second color registers or from said input buffers to said write control logic, upon the assertion of a block write enable signal. 
     
     
       4. The VRAM according to claim 1 wherein said first color register provides foreground color data for display. 
     
     
       5. The VRAM according to claim 1 wherein said second color register provides background color data for display. 
     
     
       6. A video display system comprising: a central processing unit for processing video information;   a random access memory, coupled to said CPU, that stores video data information from said CPU;   a video processor, coupled to said random access memory, that process said video display information directed from said CPU;   a video display unit, coupled to said video processor, for displaying said video display information processed by video processor;   a video random access memory (VRAM), coupled to said video processor, capable of performing opaque pattern block writes to said video display unit, said VRAM further comprising: an input buffer for receiving and holding video input information;   a first color register, coupled to said input buffer, for holding a first color value from said input buffer;   a second color register, coupled to said input buffer, for holding a second color value from said input buffer;   a first multiplexor, coupled to said first color register and said second color register;   a color selection register, coupled to said input buffer and to said first multiplexor, that uses a color selection information signal from said input buffer for gating which color value from said first color register or said second color register should be asserted;   a write control logic, coupled to said first multiplexor, for writing said selected color value and;   a mask register containing a plurality of bits, coupled to said input buffer and to said write control logic, that, based upon data from said input buffer which determine a state of each of said plurality of bits, selects which pixel location from among a plurality of pixel locations corresponding to each of said plurality of bits shall be changed based on the color value selected by said color selection register as output by said write control logic.     
     
     
       7. The system according to claim 6 wherein said registers are 8-bit registers. although wider registers, up to 32 bits, could be used. 
     
     
       8. The system according to claim 6 wherein said registers are 32-bit registers. 
     
     
       9. The system according to claim 6 further comprising a second multiplexor coupled to said first multiplexor, said input buffer, and to said write control logic for gating data either from said first and second color registers or from said input buffers to said write control logic, upon the assertion of a block write enable signal. 
     
     
       10. The system according to claim 6 wherein said first color register provides foreground color data for display. 
     
     
       11. The system according to claim 6 wherein said second color register provides background color data for display. 
     
     
       12. The system according to claim 6 further comprising a memory unit, coupled to said CPU, for storing programs to be executed by said CPU and for storing data to be processed by said CPU.