High performance semiconductor package with area array leads

Abstract

A package for high performance semiconductor devices is disclosed. The package has area array leads which can be pins, solder balls, or conductive pads. The package provides increased electrical and thermal performance at a cost that is less than that of previous technology. The packages is comprised of a printed wiring board type substrate to provide multilayer electrical connections and a thermally conductive case that encloses the top surface and the edges of the wiring substrate. The semiconductor device can be mounted directly on the thermally conductive case and connected to the substrate by any of the common methods for making first level interconnections. In the preferred embodiment, the case is comprised of copper or a copper alloy that is treated to enhance appearance and to prevent oxidation of the surface of the case. In addition to enhancing the thermal properties of the package, the copper case can also serve as a very low noise ground plane. The forged metal case with integral design features and appropriate surface finishes significantly enhance the appearance and perceived value of the package.

I claim: 
     
       1. A package for a semiconductor device comprising an enclosure, a connecting means for electrically connecting between said semiconductor device and an interconnecting means, said interconnecting means for electrically interconnecting said connecting means to another electronic system; said connecting means comprising in combination: (a) a substantially planar structure having a first surface and a second surface, said first surface being separated from said second surface by a thickness;   (b) a plurality of attachment pads, arrayed on said first surface, for forming an attachment between said connecting means and said enclosure;   (c) a plurality of first level interconnect pads, arrayed on said connecting means, for establishing electrical connections from said semiconductor device to said connecting means;   (d) a mounting means for mounting said semiconductor device such that the thermal resistance between said semiconductor device and said enclosure is reduced and said semiconductor device is positioned substantially concentric with respect to the array of said plurality of first level interconnect pads, and with the active surface of said semiconductor device substantially parallel to the major surfaces of said connecting means; and   (e) a plurality of electrically conductive members, arranged to distribute electrical signals among said first level interconnect pads and said interconnecting means, said electrically conductive members being supported and separated by an electrically insulating material;   said interconnecting means comprising an array of contacting structures which are accessible from said second surface of said connecting means and are in electrical contact with said electrically conductive members;   said enclosure comprising in combination:   (a) a structure comprised of thermally conductive material and sized to substantially enclose said first surface and the edges of said connecting means, having an exterior surface and an interior surface; and   (b) an attachment means for mounting said connecting means to said interior surface comprising a plurality of pedestals positioned such that individual ones of the plurality of pedestals correspond with individual ones of the plurality of attachment pads of said connecting means;   said connecting means being attached to the interior surface of said enclosure by an adhesive material between the attachment means of said enclosure and the attachment pads of said connecting means;   whereby providing a package for a high performance semiconductor device that can be produced at reduced cost while providing electrical, thermal and cosmetic properties that are superior to current art.   
     
     
       2. The package of claim 1 wherein said contacting structures are chosen from the group consisting of pins, columns, balls, bumps and pads. 
     
     
       3. The package of claim 1 wherein said thermally conductive material is selected from the group consisting of copper, copper alloys, aluminum, aluminum alloys, and thermally conductive resinous materials. 
     
     
       4. The package of claim 1 wherein said connecting means is a printed circuit board. 
     
     
       5. The package of claim 1 wherein said adhesive material is solder. 
     
     
       6. The package of claim 1 wherein said adhesive material is epoxy. 
     
     
       7. The package of claim 1 wherein said mounting means comprises an aperture in said connecting means exposing a surface of said enclosure which is substantially parallel to the surfaces of said connecting means. 
     
     
       8. The package of claim 1 wherein said mounting means comprises a plurality of first level interconnect pads disposed on a surface of said connecting means in an array to match the respective solder bumps of a predetermined semiconductor device intended for flip chip assembly. 
     
     
       9. The package of claim 1 wherein said mounting means comprises a portion of said second surface of said connecting means.