Current limiting devices to reduce leakage, photo, or stand-by current in an integrated circuit

Abstract

A current limiting circuit 12 is placed between a supply voltage, Vcc and circuitry 14. Current limiting circuit 12 supplies sufficient current for normal operation of circuitry 14, but less than would be required if all potentially conductive paths of circuitry 14 were active at one time. Current limiting circuit 12 may be operable to either limit or interrupt the flow of current between Vcc and circuitry 14 in response to a control signal. A second current limiting device 16 may be placed between circuitry 14 and a second supply voltage, VSS.

What is claimed is: 
     
       1. An integrated circuit comprising: a. a functional circuit comprising a plurality of circuit elements, each of said circuit elements operable to provide a conductive path, wherein less than all of said plurality of circuit elements are active at any one time; and   b. a current limiting circuit in addition to said functional circuit connected between said plurality of circuit elements and a first voltage, wherein said current limiting circuit comprises at least one transistor and is operable to supply less than a selected current level to said plurality of elements, said current level being less than a current level required to operate all of said plurality of circuit elements, and wherein a plurality of said plurality of circuit elements are each connected between said current limiting transistor and an output node of the functional circuit.   
     
     
       2. The integrated circuit of claim 1, wherein said current limiting circuit is responsive to a control signal such that said current limiting circuit is operable to change from a first conductivity state to a second conductivity state in response to said control signal. 
     
     
       3. The integrated circuit of claim 2, wherein said control signal comprises a chip enable signal. 
     
     
       4. The integrated circuit of claim 2, wherein said control signal comprises a block enable signal. 
     
     
       5. The integrated circuit of claim 2 wherein said control signal comprises a transient dose detection signal. 
     
     
       6. A semiconductor device comprising: a logic circuit having a plurality of potentially conducting paths connected in parallel between an output node and a current limiting device, wherein said current limiting device is connected to a first voltage such that said current limiting device supplies current to said logic circuit and wherein said current limiting device is responsive to transient dose detection signal such that said current limiting device is operable to interrupt power to said logic circuit in response to a standby condition indicated by said transient dose detection signal.   
     
     
       7. The device of claim 6, wherein said first voltage is a supply voltage. 
     
     
       8. The device of claim 6, wherein said first voltage is a ground voltage. 
     
     
       9. The device of claim 6, wherein said current limiting device comprises a CMOS transistor. 
     
     
       10. An integrated circuit comprising: a. a memory array;   b. logic circuitry comprising a plurality of circuit elements; and   c. a current limiting device connected between said logic circuitry and a first voltage, wherein said current limiting device is connected to each of said plurality of circuit elements and wherein said current limiting device limits the current to said plurality of circuit elements to a level less than that required for all of said plurality of circuit elements to be active at one time.   
     
     
       11. The integrated circuit of claim 10, wherein said plurality of circuit elements comprises a plurality of wordline drivers. 
     
     
       12. The integrated circuit of claim 10, wherein said plurality of circuit elements comprises a sense amplifier and a bit-line driver. 
     
     
       13. The integrated circuit of claim 10, wherein less than all of said plurality of circuit elements are active at any one time. 
     
     
       14. The integrated circuit of claim 10, where said circuitry is CMOS circuitry. 
     
     
       15. A method of selectively limiting the current to a circuit comprising the steps off a. providing a current limiting transistor between a supply voltage and said circuit;   b. detecting whether a current level through an off transistor exceeds a threshold level;   c. providing a first signal level to a gate of said current limiting transistor when said current level is less than said threshold level such that said current limiting transistor connects said supply voltage to said circuit; and   d. providing a second signal level to said gate when said current level exceeds said threshold level such that said current limiting transistor interrupts said supply voltage from said circuit.   
     
     
       16. The method of claim 15, wherein said current limiting transistor comprises a CMOS transistor. 
     
     
       17. The method of claim 15, further comprising the step of placing said circuit is a preferred state when said current limiting transistor interrupts said supply voltage from said circuit. 
     
     
       18. A method of reducing the probability of data corruption in an integrated circuit, comprising the steps of: a. providing a plurality of field effect transistors connected in parallel;   b. providing a current limiting transistor connected between said plurality of field effect transistors and a first voltage, wherein said current limiting transistor has a width less than the total width of said plurality of field effect transistors;   c. conducting current through said current limiting transistor;   d. limiting said current to a threshold current level wherein the probability of data corruption is reduced by said step of limiting said current to said threshold current level.   
     
     
       19. The method of claim 18 wherein said threshold current level is less than a full current level required to transition all of said plurality of field effect transistors. 
     
     
       20. The method of claim 18 wherein said threshold current level is approximately equal to a single current level required to transition only one of said plurality of field effect transistors. 
     
     
       21. The method of claim 18 wherein said step of conducting current comprises the step of grounding a gate of said current limiting transistor. 
     
     
       22. The method of claim 18 wherein said step of conducting current comprises the step of connecting a chip enable signal to a gate of said current limiting transistor. 
     
     
       23. The method of claim 18 wherein said step of conducting current comprises the step of connecting a block enable signal to a gate of said current limiting transistor. 
     
     
       24. An integrated circuit comprising: a functional circuit comprising a plurality of circuit elements, each of said circuit elements operable to provide a conductive path, wherein less than all of said plurality of circuit elements are active at any one time;   a current limiting circuit in addition to said functional circuit connected between said plurality of circuit elements and a first voltage, wherein said current limiting circuit comprises at least one transistor having a first conductivity state operable to supply a selected current level to said plurality of circuit elements, said selected current level being sufficient to operate at least one of said plurality of circuit elements but less than all of said plurality of circuit elements; and   wherein said current limiting circuit is responsive to a binary control signal for changing said current limiting circuit from said first conductivity state to a second conductivity state wherein said current limiting circuit is operable to supply a reduced current level less than that required to operate one of said plurality of circuit elements.   
     
     
       25. The integrated circuit of claim 24, wherein said binary control signal comprises a chip enable signal. 
     
     
       26. The integrated circuit of claim 24, wherein said binary control signal comprises a block enable signal. 
     
     
       27. The integrated circuit of claim 24, wherein said binary control signal comprises a transient dose detection signal.