Adaptive video signal processing apparatus

Abstract

A processing apparatus which adaptively performs image compensation and encoding/expansion and decoding processing such as discrete cosine transformation (DCT)/inverse discrete cosine transformation (IDCT), inner product computation, image data addition, and image data differential processing, etc. for blocks of image data of a size of m×n, which is provided with (a) plurality of parallel processing units 1 to 4 each of which performs addition, subtraction, various types of logical computations, comparison of magnitude, computation of absolute values of differences, and butterfly addition·subtraction processing, performs multiplication, and performs accumulation; (b) mutually connected pipeline memories 5 to 7 which are disposed so as to connect adjoining processing units among these processing units; and (c) data selectors 41 to 44 which selectively apply input data to the processing units 1 to 4, wherein adjoining processing units are coupled via the mutually connected pipeline memories and wherein an internal pipeline memory in the aforesaid processing unit is selected to constitute a predetermined data flow path, thereby to perform DCT or other desired video signal processing.

I claim: 
     
       1. An adaptive video signal processing apparatus for adaptively performing image compression and encoding/expansion and decoding processing such as discrete cosine transformation/inverse discrete cosine transformation, quantization/inverse quantization, motion vector detection, motion compensation, inner product computation, image data addition, and image data difference processing on blocks of image data of m×n size, said processing apparatus comprising   a plurality of processing units provided in parallel, each of which having an extended arithmetic and logic unit performing addition, subtraction, various logical computations, comparison of magnitude, computation of absolute values of differences, butterfly addition and subtraction processing, a first internal pipeline memory provided at a stage after said extended arithmetic and logic unit, a multiplier unit provided at a stage after said first internal pipeline memory, a coefficient memory supplying a coefficient to said multiplier unit, a second internal pipeline memory provided at a stage after said multiplier unit, an accumulation processing unit provided at a stage after said second internal pipeline memory, and a third internal pipeline memory provided at a stage after said accumulation processing unit;   mutually connected pipeline memories disposed so as to connect adjoining processing units among these plurality of parallel processing units; and   data selectors which selectively supply the input data to said plurality of processing units, wherein   adjoining processing units are coupled via said mutually connected pipeline memories and, the internal pipeline memories in said processing units are selected to constitute a predetermined data flow path,   to thereby perform a desired video signal processing such as discrete cosine transformation, wherein said adaptive video signal processor operates by a "single instruction stream·multiple data stream (SIMD)" control system for performing multiple data stream processing by a single instruction stream.   
     
     
       2. An adaptive video signal processing apparatus as set forth in claim 1, wherein in said processing unit, said extended arithmetic and logic unit, said multiplier unit, and said accumulation processing unit perform a pipeline processing operation. 
     
     
       3. An adaptive video signal processing apparatus as set forth in claim 2, wherein each of said extended arithmetic and logic unit has: a positive/negative inverter which inverts the polarity of a first input data;   a first data selector which is provided at a stage after said positive/negative inverter and selectively outputs said first input data or said polarity-inverted first data;   an adder adding the selected Output data of said first data selector and a second input data;   a subtracter which subtracts said second input data from said first input data;   a logical processor which performs the logical processing of said first input data and said second data such as a logical OR, logical AND, exclusive logical OR, negation, etc.;   a positive/negative decision unit receiving as its input the output of said adder and said subtracter and performing the positive/negative decision;   a second data selector receiving as its inputs the outputs of said adder, said logical processor, and said positive/negative decision unit and selectively outputting a selected input;   a first output terminal connected to said second data selector; and   a second output terminal connected to the aforesaid subtracter,   any of an addition, subtraction, various types of logical computations, comparisons of magnitude, computation of absolute values of differences, and butterfly addition·subtraction processing being carried out by suitable combining of the components of the extended arithmetic and logic unit from said positive/negative inverter to said second output terminal.   
     
     
       4. An adaptive video signal processing apparatus as set forth in claim 3, wherein a terminal receiving as its input data for discrete cosine transformation processing is provided in the first-stage processing unit of said plurality of processing units; and   a terminal receiving as its input the data for inverse discrete cosine transformation processing is provided in the final stage processing unit of said plurality of processing units.   
     
     
       5. An adaptive video signal processing apparatus as set forth in claim 4, wherein a route is established so that, when the discrete cosine transformation processing is carried out by performing a butterfly computation and pipeline memory processing a plurality of times using blocks of image data of m×n size, (a) said discrete cosine transformation processing data is input to said extended arithmetic and logic units in a plurality of processing units excluding said final stage processing unit and the processing results in said extended arithmetic and logic units are output to neighboring mutually connected pipeline memories, and   (b) the data of the final stage of the mutually connected pipeline memories is input to the multiplier units in all processing units and the multiplication results are accumulated in said accumulation unit.   
     
     
       6. An adaptive video signal processing apparatus as set forth in claim 4, wherein the route is established so that, when discrete cosine transformation processing is carried out by performing pipeline memory processing and butterfly computation a plurality of times using blocks of image data of m×n size, (a) said discrete cosine transformation processing data is input to the multiplier units in all processing units and the results of multiplication are accumulated at the accumulation unit,   (b) the output is input to said extended arithmetic and logic units in the plurality of processing units excluding said initial stage processing unit and the results of processing in said extended arithmetic and logic units are output to mutually connected and neighboring pipeline memories.   
     
     
       7. An adaptive video signal processing apparatus as set forth in claim 1, wherein the route is established so that, when quantization processing is carried out, (a) an output terminal of a multiplier unit of a first processing unit in adjoining processing units is connected to the input terminal of the multiplier unit of the second processing unit,   (b) the result of multiplication of said second multiplier unit is input to said accumulation unit at a stage after said second multiplier unit, and   (c) the data to be quantized is input to said first multiplier unit.     
     
     
       8. An adaptive video signal processing apparatus as set forth in claim 1, wherein the route is established so that, when inverse quantization processing is carried out, (a) an output terminal of a multiplier unit of a first processing unit in adjoining processing units is connected to the input terminal of the multiplier unit of the second processing unit,   (b) the result of multiplication of said second multiplier unit is input to an accumulation unit at a stage after said second multiplier unit, and   (c) the data to be inversely quantized and a constant are input to the first processing unit and the result of the computation is input to the first multiplier unit.     
     
     
       9. An adaptive video signal processing apparatus as set forth in claim 1, wherein the route is established so that, when processing for detection of a motion vector is performed, (a) said extended arithmetic and logic units in all processing units are connected to the accumulation processing unit and   (b) two sets of data covered by the processing for detection of the motion vector are input to said extended arithmetic and logic units.     
     
     
       10. An adaptive video signal processing apparatus as set forth in claim 1, wherein the route is established so that, when processing is performed for virtual pixel production in motion compensation, (a) said extended arithmetic and logic units in all processing units are connected to said accumulation processing unit and   (b) two sets of data covered by the processing for the production of a virtual pixel in motion compensation are input to said extended arithmetic and logic units.     
     
     
       11. An adaptive video signal processing apparatus as set forth in claim 1, wherein the route is established so that, when processing is performed for predictive pixel production in motion compensation, (a) the output of one multiplier unit of adjoining processing units is supplied to one input terminal of the other extended arithmetic and logic unit,   (b) the output of the other multiplier unit is supplied to the other input terminal of said other extended arithmetic and logic unit, and   (c) the result of computation of said other extended arithmetic and logic unit is accumulated in the other accumulation unit.     
     
     
       12. An adaptive video signal processing apparatus as set forth in claim 1, wherein the route is established so that, when processing is performed for computation of the inner product, (a) the data covered by the processing of the inner product is input to the multiplier units in all processing units and   (b) the results of multiplication are accumulated in the corresponding accumulation unit.     
     
     
       13. An adaptive video signal processing apparatus as set forth in claim 1, wherein the route is established so that, when processing is performed for image data addition or image data subtraction, the data to be processed is input to said extended arithmetic and logic units in all processing units and the results of the processing are output.   
     
     
       14. An adaptive video signal processing apparatus for adaptively performing image compression and encoding/expansion and decoding processing such as discrete cosine transformation/inverse discrete cosine transformation, quantization/inverse quantization, motion vector detection, motion compensation, inner product computation, image data addition, and image data difference processing on blocks of image data of m×n size, said processing apparatus comprising   a plurality of processing units provided in parallel, each of which having an extended arithmetic and logic unit performing addition, subtraction, various logical computations, comparison of magnitude, computation of absolute values of differences, butterfly addition and subtraction processing, a first internal pipeline memory provided at a stage after said extended arithmetic and logic unit, a multiplier unit provided at a stage after said first internal pipeline memory, a coefficient memory supplying a coefficient to said multiplier unit, a second internal pipeline memory provided at a stage after said multiplier unit, an accumulation processing unit provided at a stage after said second internal pipeline memory, and a third internal pipeline memory provided at a stage after said accumulation processing unit;   mutually connected pipeline memories disposed so as to connect adjoining processing units among these plurality of parallel processing units;   data selectors which selectively supply the input data to said plurality of processing units, wherein   adjoining processing units are coupled via said mutually connected pipeline memories and, the internal pipeline memories in said processing units are selected to constitute a predetermined data flow path,   to thereby perform a desired video signal processing such as discrete cosine transformation, wherein said adaptive video signal processor operates by a "single instruction stream·multiple data stream (SIMD)" control system for performing multiple data stream processing by a single instruction stream,   wherein in said processing unit, said extended arithmetic and logic unit, said multiplier unit, and said accumulation processing unit perform a pipeline processing operation, and   wherein each of said extended arithmetic and logic unit has: a positive/negative inverter which inverts the polarity of a first input data;   a first data selector which is provided at a stage after said positive/negative inverter and selectively outputs said first input data or said polarity-inverted first data;   an adder adding the selected output data of said first data selector and a second input data;   a subtracter which subtracts said second input data from said first input data;   a logical processor which performs the logical processing of said first input data and said second data such as a logical OR, logical AND, exclusive logical OR, negation, etc.;   a positive/negative decision unit receiving as its input the output of said adder and said subtracter and performing the positive/negative decision;   a second data selector receiving as its inputs the outputs of said adder, said logical processor, and said positive/negative decision unit and selectively outputting a selected input;   a first output terminal connected to said second data selector; and   a second output terminal connected to the aforesaid subtracter,   any of an addition, subtraction, various types of logical computations, comparisons of magnitude, computation of absolute values of differences, and butterfly addition·subtraction processing being carried out by suitable combining of the components of the extended arithmetic and logic unit from said positive/negative inverter to said second output terminal.     
     
     
       15. An adaptive video signal processing apparatus as set forth in claim 14, wherein a terminal receiving as its input data for discrete cosine transformation processing is provided in the first-stage processing unit of said plurality of processing units; and   a terminal receiving as its input the data for inverse discrete cosine transformation processing is provided in the final stage processing unit of said plurality of processing units.   
     
     
       16. An adaptive video signal processing apparatus as set forth in claim 15, wherein a route is established so that, when the discrete cosine transformation processing is carried out by performing a butterfly computation and pipeline memory processing a plurality of times using blocks of image data of m×n size, (a) said discrete cosine transformation processing data is input to said extended arithmetic and logic units in a plurality of processing units excluding said final stage processing unit and the processing results in said extended arithmetic and logic units are output to neighboring mutually connected pipeline memories, and   (b) the data of the final stage of the mutually connected pipeline memories is input to the multiplier units in all processing units and the multiplication results are accumulated in said accumulation unit.   
     
     
       17. An adaptive video signal processing apparatus as set forth in claim 15, wherein the route is established so that, when discrete cosine transformation processing is carried out by performing pipeline memory processing and butterfly computation a plurality of times using blocks of image data of m×n size, (a) said discrete cosine transformation processing data is input to the multiplier units in all processing units and the results of multiplication are accumulated at the accumulation unit,   (b) the output is input to said extended arithmetic and logic units in the plurality of processing units excluding said initial stage processing unit and the results of processing in said extended arithmetic and logic units are output to mutually connected and neighboring pipeline memories.   
     
     
       18. An adaptive video signal processing apparatus as set forth in claim 14, wherein the route is established so that, when quantization processing is carried out, (a) an output terminal of a multiplier unit of a first processing unit in adjoining processing units is connected to the input terminal of the multiplier unit of the second processing unit,   (b) the result of multiplication of said second multiplier unit is input to said accumulation unit at a stage after said second multiplier unit, and   (c) the data to be quantized is input to said first multiplier unit.     
     
     
       19. An adaptive video signal processing apparatus as set forth in claim 14, wherein the route is established so that, when inverse quantization processing is carried out, (a) an output terminal of a multiplier unit of a first processing unit in adjoining processing units is connected to the input terminal of the multiplier unit of the second processing unit,   (b) the result of multiplication of said second multiplier unit is input to an accumulation unit at a stage after said second multiplier unit, and   (c) the data to be inversely quantized and a constant are input to the first processing unit and the result of the computation is input to the first multiplier unit.     
     
     
       20. An adaptive video signal processing apparatus as set forth in claim 14, wherein the route is established so that, when processing for detection of a motion vector is performed, (a) said extended arithmetic and logic units in all processing units are connected to the accumulation processing unit and   (b) two sets of data covered by the processing for detection of the motion vector are input to said extended arithmetic and logic units.     
     
     
       21. An adaptive video signal processing apparatus as set forth in claim 14, wherein the route is established so that, when processing is performed for virtual pixel production in motion compensation, (a) said extended arithmetic and logic units in all processing units are connected to said accumulation processing unit and   (b) two sets of data covered by the processing for the production of a virtual pixel in motion compensation are input to said extended arithmetic and logic units.     
     
     
       22. An adaptive video signal processing apparatus as set forth in claim 14, wherein the route is established so that, when processing is performed for predictive pixel production in motion compensation, (a) the output of one multiplier unit of adjoining processing units is supplied to one input terminal of the other extended arithmetic and logic unit,   (b) the output of the other multiplier unit is supplied to the other input terminal of said other extended arithmetic and logic unit, and   (c) the result of computation of said other extended arithmetic and logic unit is accumulated in the other accumulation unit.     
     
     
       23. An adaptive video signal processing apparatus as set forth in claim 14, wherein the route is established so that, when processing is performed for computation of the inner product, (a) the data covered by the processing of the inner product is input to the multiplier units in all processing units and   (b) the results of multiplication are accumulated in the corresponding accumulation unit.     
     
     
       24. An adaptive video signal processing apparatus as set forth in claim 14, wherein the route is established so that, when processing is performed for image data addition or image data subtraction, the data to be processed is input to said extended arithmetic and logic units in all processing units and the results of the processing are output.