Flash memory array with self-limiting erase

Abstract

A flash memory array with self-limiting erase for preventing over-erasure utilizes a self-limiting-erase floating gate transistor coupled to the memory array or to each row of memory cells. The self-limiting-erase transistor has a smaller threshold voltage than the memory cells. When all memory cells or one row of memory cells are erased, the drain of the transistor is connected via a feedback path to all word lines of the memory array or to the corresponding word line for that row of memory cells. When the self-limiting-erase transistor is turned on due to full erasing, the potential of the word lines is pulled up to the erasing voltage which is applied at the sources of the memory cells, thereby the erase operation is stopped automatically.

What is claimed is: 
     
       1. A non-volatile memory array comprising: a plurality of memory cells arranged in rows and columns, each memory cell having a source, a drain, a floating gate and a control gate, the control gates of all memory cells in each row being interconnected by a word line, the drains of all memory cells in each column being interconnected by a bit line, and the sources of said memory cells being interconnected by a source line;   a switching element;   a self-limiting-erase floating gate transistor disposed in said memory array, having a control gate coupled to said word lines via said switching element, and a source coupled to said source line; and   feedback means for connected the drain of said self-limiting-erase floating gate transistor to said word lines in order to limit the erase operation when said memory cells are erased.   
     
     
       2. The memory array as claimed in claim 1, wherein said feedback means includes an impedance element connected between the drain of said self-limiting-erase floating gate transistor and said word lines. 
     
     
       3. The memory array as claimed in claim 1, wherein said memory cells have a higher threshold voltage than that of said self-limiting-erase floating gate transistor. 
     
     
       4. The memory array as claimed in claim 3, wherein the difference between the threshold voltages of said memory cells and said self-limiting-erase floating gate transistor is in the range of about 0.1 to 1 volts. 
     
     
       5. The memory array as claimed in claim 3, wherein the threshold voltage difference is obtained by implanting ions of different dosages into the channel regions of said memory cells and said self-limiting-erase floating gate transistor. 
     
     
       6. The memory array as claimed in claim 3, wherein the threshold voltage difference is obtained by electrically programming said memory cells to increase their threshold voltages. 
     
     
       7. The memory array as claimed in claim 1, wherein said memory array is a flash memory cell array. 
     
     
       8. The memory array as claimed in claim 1, wherein said switching element is an OR gate having input terminals connected to said word lines, and an output terminal connected to the control gate of said self-limiting-erase floating gate transistor.