Output voltage controlling circuit in a negative charge pump

Abstract

The present invention relates to an output voltage controlling circuit in the negative charge pump which allows the output voltage of the negative charge pump to be controlled at a desired voltage level using a breakdown point of the PMOS transistor for high voltage by a PMOS transistor for high voltage connected between the output terminal of the negative charge pump and a reference voltage generation circuit.

What is claimed is: 
     
       1. An output voltage controlling circuit of a negative charge pump comprising: a first controlling circuit connected between an input terminal and an output terminal of said negative charge pump, wherein an enable signal is received at an input terminal of said first controlling circuit and the input terminal of said negative charge pump, said first controlling circuit including: (a) a PMOS transistor connected between a voltage supply source Vcc and said output terminal of said negative charge pump, and having gate electrode, a source electrode and a drain electrode and   (b) an inverter connected between said gate electrode of said PMOS transistor and said input terminal of said negative charge pump;     a second controlling circuit connected to said output terminal of said negative charge pump;   a reference voltage generation circuit generating a reference voltage according to an output signal of said second controlling circuit;   a third controlling circuit connected to said reference voltage generation circuit, and for receiving said output signal of said second controlling circuit; and   a voltage controlling circuit connected to said output terminal of said negative charge pump, and for receiving an output signal of said third controlling circuit.   
     
     
       2. An output voltage controlling circuit of a negative charge pump comprising: a first controlling circuit connected between an input terminal and an output terminal of said negative charge pump, wherein an enable signal is received at an input terminal of said first controlling circuit and the input terminal of said negative charge pump;   a second controlling circuit connected to said output terminal of said negative charge pump, said second controlling circuit including: (a) a first PMOS transistor connected between a node A and a ground voltage Vss, and said first PMOS transistor receiving an output signal of said negative charge pump,   (b) a second PMOS transistor connected between said output terminal of said negative charge pump and said node A and   (c) an inverter connected to node A;     a reference voltage generation circuit generating a reference voltage according to an output signal of said second controlling circuit;   a third controlling circuit connected to said reference voltage generation circuit, and for receiving said output signal of said second controlling circuit, wherein an output signal of said inverter is inputted to said reference voltage generation circuit and said third controlling circuit; and   a voltage controlling circuit connected to said output terminal of said negative charge pump, and for receiving an output signal of said third controlling circuit.   
     
     
       3. An output voltage controlling circuit of a negative charge pump comprising: a first controlling circuit connected between an input terminal and an output terminal of said negative charge pump, wherein an enable signal is received at an input terminal of said first controlling circuit and the input terminal of said negative charge pump;   a second controlling circuit connected to said output terminal of said negative charge pump;   a reference voltage generation circuit generating a reference voltage according to an output signal of said second controlling circuit,said reference voltage generation circuit including: (a) a NMOS transistor for receiving said output signal of said second controlling circuit,   (b) a plurality of reference resistors connected in series between a drain electrode of said NMOS transistor and a voltage supply source Vcc and   (c) a pair of PMOS transistors connected in series between said voltage supply Vcc and a ground voltage Vss;     a third controlling circuit connected to said reference voltage generation circuit, and for receiving said output signal of said second controlling circuit; and   a voltage controlling circuit connected to said output terminal of said negative charge pump, and for receiving an output signal of said third controlling circuit.   
     
     
       4. An output voltage controlling circuit of a negative charge pump comprising: a first controlling circuit connected between an input terminal and an output terminal of said negative charge pump, wherein an enable signal is received at an input terminal of said first controlling circuit and the input terminal of said negative charge pump;   a second controlling circuit connected to said output terminal of said negative charge pump;   a reference voltage generation circuit generating a reference voltage according to an output signal of said second controlling circuit;   a third controlling circuit connected to said reference voltage generation circuit, and for receiving said output signal of said second controlling circuit, said third controlling circuit including: (a) an inverter for inverting said output signal of said second controlling circuit,   (b) a second PMOS transistor receiving an output signal of said inverter and connected between said reference voltage generation circuit and a node B and   (c) a first PMOS transistor connected between a voltage supply source Vcc and said node B, and receiving said output signal of said second controlling circuit;     a voltage controlling circuit connected to said output terminal of said negative charge pump, and for receiving an output signal of said third controlling circuit.   
     
     
       5. An output voltage controlling circuit of a negative charge pump comprising: a first controlling circuit connected between an input terminal and an output terminal of said negative charge pump, wherein an enable signal is received at an input terminal of said first controlling circuit and the input terminal of said negative charge pump;   a second controlling circuit connected to said output terminal of said negative charge pump;   a reference voltage generation circuit generating a reference voltage according to an output signal of said second controlling circuit;   a third controlling circuit connected to said reference voltage generation circuit, and for receiving said output signal of said second controlling circuit; and   a voltage controlling circuit connected to said output terminal of said negative charge pump, and for receiving an output signal of said third controlling circuit, said voltage controlling circuit including: (a) a PMOS transistor for high voltage having a gate electrode connected to a ground voltage Vss, a source electrode connected to said output terminal of said negative charge pump, a floated drain electrode and a N-well connected to a node B of said third controlling circuit, said source electrode and said N-well are operated as P-N junction diode.     
     
     
       6. An output voltage controlling circuit in a negative charge pump comprising: a PMOS transistor having a gate electrode, a source electrode and a drain electrode which are formed on a N-well with said gate electrode being grounded, said drain electrode being floated and said source electrode being connected to an output terminal of said negative charge pump;   a first controlling circuit connected between an input terminal of said negative charge pump and said output terminal of said negative charge pump, wherein an enable signal is received at an input terminal of said first controlling circuit and the input terminal of said negative charge pump; and   a bias supplying means connected between said output terminal of said negative charge pump and said N-well to control an output voltage of said negative charge pump, said bias supplying means having a second controlling circuit connected to said output terminal of said negative charge pump, a reference voltage generation circuit generating a reference voltage according to an output signal of said second controlling circuit, and a third controlling circuit connected between said reference voltage generation circuit and said N-well of said PMOS transistor, wherein said third controlling circuit is controlled by said output signal of said second controlling circuit.   
     
     
       7. The controlling circuit of claim 6, wherein said first controlling circuit comprises: a PMOS transistor having a gate electrode, a drain electrode and a source electrode with said source electrode being connected to a voltage supply source and said drain electrode being connected to said output terminal of said negative charge pump; and   an inverter connected between said gate electrode of said PMOS transistor and said input terminal of said negative charge pump.   
     
     
       8. The controlling circuit including the second controlling circuit as claimed in claim 6, and further comprising a connecting node, wherein: a first PMOS transistor connected between ground and said node, with said first PMOS transistor being turned on depending upon said output terminal, of said negative charge pump;   a second PMOS transistor connected between said node and said output terminal of said negative charge pump, wherein a gate electrode of said second PMOS transistor is connected to said node; and   an inverter to invert voltage potential of said node, wherein an output signal of said inverter is inputted to said reference voltage generation circuit and said third controlling circuit.   
     
     
       9. The controlling circuit of claim 6, wherein said reference voltage generation circuit comprises: first and second PMOS transistors connected, in series, between a voltage supply source and ground;   a first resistor connected between said voltage supply source and a gate electrode of said first PMOS transistor;   a second resistor connected between said gate electrode of said first and said second PMOS transistors; and   a third resistor and a NMOS transistor connected, in series, between said gate electrode of said second PMOS transistor and said ground, with a gate electrode of said NMOS transistor receiving said output signal of said second controlling circuit.   
     
     
       10. The controlling circuit of claim 6, wherein said third controlling circuit comprises: a first PMOS transistor connected between said N-well of said PMOS transistor and a voltage supply source;   a second PMOS transistor connected between said N-well of said PMOS transistor and said reference voltage generation circuit; and   an inverter connected between said second controlling circuit and a gate electrode of said second PMOS transistor.   
     
     
       11. The controlling circuit of claim 6, wherein said source electrode and said N-well of said PMOS transistor are operated as P-N junction diode.