Method of manufacture of multi-cell integrated circuit architecture

Abstract

A standard cell topography has a generally rectangular topography, circumscribed by a set of four mutually orthogonal cell boundary edges. Coupled in circuit with a standard AND gate circuit within the cell are a pair of sense nodes for testing the AND gate. The sense MOSFETs are adjacent to opposite cell edges and are connected to respective sense nodes. First and second parallel metallic control links, which are used to gate the sense MOSFETs, extend the width of the cell between opposing cell boundary edges, so as to facilitate placement of the cells in boundary edge-abutting relationship, so that abutting control links may effectively form continuous runs through all the cells of a respective row of cells. A first output terminal of the first sense MOSFET is adjacent to one boundary edge and a second output node of the second terminal of the second sense MOSFET is adjacent to the other opposing cell boundary edge. This edge proximity placement of the output nodes of the sense MOSFETs facilitates coupling of the MOSFET output nodes to boundary edge-located sense terminals, which intersect the cell boundary edges.

What is claimed: 
     
       1. A method of manufacture of a semiconductor circuit cell architecture, in accordance with a cell topography that facilitates placement of respective cells in abutting relationship in a multiple cell layout, and testing of said respective cells, prior to routing interconnect material to conductive links within and to selected nodes among said respective cells, said method of manufacture comprising the steps of: (a) forming a semiconductor circuit at a first physical location of a generally rectangular physical topography geometry of a semiconductor cell, said generally rectangular physical topography geometry of said semiconductor cell having a plurality of cell boundary edges, said semiconductor circuit having an input terminal to which an input signal is applied, an output terminal from which an output signal is derived, first and second sense nodes, for monitoring an operation of said semiconductor circuit, and first and second sense output terminals, said first and second sense output terminals intersecting first and second opposite ones of said plurality of cell boundary edges;   (b) forming first and second controllable semiconductor switching devices at a second physical location of said generally rectangular physical topography geometry of said semiconductor cell, adjacent to said first physical location of said generally rectangular physical topography geometry of said semiconductor cell, said first and second controllable semiconductor switching devices being controllably operative to respectively couple said first and second sense nodes to said first and second sense output terminals, and wherein said first controllable semiconductor switching device has a first output node physically located in proximity with a first cell boundary edge, a first input node physically located adjacent to said semiconductor circuit, so as to facilitate placement of a first connection link to said first sense node of said semiconductor circuit, and a first control node, and wherein said second controllable semiconductor switching device has a second output node physically located in proximity with a second cell boundary edge, a second input node located physically adjacent to said semiconductor circuit, so as to facilitate physical placement of a second connection link to said second sense node of said semiconductor circuit, and a second control node, and wherein said first control node, in response to receiving a control signal supplied by a test circuit, controllably causes said first controllable semiconductor switching device to provide a conductive path between said first sense node and said first sense output terminal, and wherein said second control node, in response to receiving a control signal supplied by said test circuit, controllably causes said second controllable semiconductor switching device to provide a conductive path between said second sense node and said second sense output terminal;   (c) physically forming first and second conductive control links at a third physical location of said semiconductor substrate, said first and second conductive control links being disposed parallel to one another and extending between said first and second opposite cell boundary edges, so as to allow physical placement of respective cells in cell boundary edge-abutting relationship, in order to effectively form continuous physical runs of each of said first and second conductive control links through mutually abutting cells;   (d) prior to routing interconnect material among respective ones of a plurality of said semiconductor cells and prior to forming control node connection links that serve to electrically selectively interconnect control nodes of said first and second controllable semiconductor switching devices and selected ones of said first and second conductive control links, placing a plurality of said semiconductor cells in abutting relationship, such that the first cell boundary edge of a respective semiconductor cell abuts the second semiconductor cell boundary edge of another semiconductor cell, with first and second sense nodes of abutting cells being disposed adjacent to one another, to be connected to the same output terminal interconnect link; and   (e) physically forming first and second control node connection links so as to electrically interconnect said respective first and second control nodes of said first and second controllable semiconductor switching devices and selected ones of said first and second conductive control links, and physically routing output terminal interconnect links among selected abutting cells and connecting said output terminal interconnect links to selected first and second sense nodes, such that first and second controllable semiconductor switching devices, whose respective first and second sense nodes are connected to the same output terminal interconnect link, are connected to different control node connection links.   
     
     
       2. A method according to claim 1, wherein said semiconductor circuit cell architecture has a third cell boundary edge which intersects said first and second cell boundary edges, and wherein step (c) comprises physically forming said first and second conductive control links parallel to one another and said third cell boundary edge. 
     
     
       3. A method according to claim 1, wherein step (c) comprises physically forming said first and second control links in proximity with said first and second controllable semiconductor switch devices. 
     
     
       4. A method according to claim 1, wherein said first and second controllable semiconductor switch devices comprise first and second field effect transistors, respectively, and wherein each of said first and second field effect transistors has one of its source and drain electrodes coupled to a respective one of said first and second sense nodes, and the other of its source and drain electrodes coupled to a respective one of said first and second output nodes, and wherein step (e) comprises forming said first control node connection links so as to be electrically connected to the gate electrode of said first field effect transistor, and forming said second control node connection link so as to be electrically connected to the gate electrode of said second field effect transistor. 
     
     
       5. A method of manufacture of a multi-cell integrated circuit architecture, in accordance with a cell topography that facilitates placement of respective cells, in abutting relationship in a multiple cell layout, and testing of said respective cells, prior to routing interconnect material to conductive links within and to selected nodes among said respective cells, said method of manufacture comprising the steps of: (a) forming a matrix of rows and columns of semiconductor circuit cells in a semiconductor substrate, such that a respective row of cells contains cells arranged in edge-to-edge abutment with one another, and wherein each of plural ones of said cells have a standard cell configuration that comprises: (i) a generally rectangular semiconductor topography geometry defined by four mutually orthogonal cell boundary edges and including a semiconductor circuit disposed at a first physical location thereof, said semiconductor circuit having an input terminal to which an input signal is applied, an output terminal from which an output signal is derived, first and second sense nodes for monitoring an operation of said semiconductor circuit, and first and second sense output terminals, first and second sense output terminals intersecting said first and second cell boundary edges, thereby allowing sense output terminals of cells of adjacent rows of a matrix of cells to be electrically interconnected by a conductive layer therebetween physically extending in a direction generally parallel to edge-to-edge abutment of cells of a respective row of cells; and   (ii) first and second controllable semiconductor switching devices, located at a second physical location of said generally rectangular semiconductor topography geometry, adjacent to said first physical location, and which are controllably operative to respectively couple said first and second sense nodes to said first and second sense output terminals, said first controllable semiconductor switching device having a first output node located in physical proximity with a first cell boundary edge, a first input node physically located adjacent to said semiconductor circuit, so as to facilitate placement of a first connection link to said first sense node of said semiconductor circuit, and a first control node, said second controllable semiconductor switching device having a second output node located in physical proximity with a second cell boundary edge, opposite to said first cell boundary edge, a second input node physically located adjacent to said semiconductor circuit, so as to facilitate physical placement of a second connection link to said second sense node of said semiconductor circuit, and a second control node, and wherein said first control node, in response to receiving a control signal supplied by a test circuit, controllably causes said first controllable semiconductor switching device to provide a conductive path between said first sense node and said first sense output terminal, and wherein said second control node, in response to receiving a control signal supplied by said test circuit, controllably causes said second controllable semiconductor switching device to provide a conductive path between said second sense node and said second sense output terminal;     (b) forming first and second conductive control links extending parallel to one another across said standard cell between said first and second opposite cell boundary edges, so as to afford placement of respective cells in cell boundary edge-abutting relationship, in order to effectively form continuous runs of each of said first and second conductive control links through mutually abutting cells;   (c) prior to forming control node connection links which selectively electrically interconnect control nodes of said first and second controllable switching devices and selected ones of said first and second conductive control links, and prior to routing interconnect material among respective ones of a plurality of said standard cells, placing a plurality of said standard cells in abutting relationship, such that the first cell boundary edge of one cell abuts the second cell boundary edge of another cell, with first and second sense nodes of abutting cells being disposed adjacent to one another for connection to the same output terminal interconnect line;   (d) forming first and second control node connection links to interconnect said respective first and second control nodes of said first and second controllable semiconductor switching devices and selected ones of said first and second conductive control links, such that first and second controllable semiconductor switching devices, whose first and second sense nodes are connected to the same sense output terminal interconnect link, are connected to different control node connection links; and   (e) selectively routing sense output terminal interconnection links among the first and second sense output terminals of cells of adjacent rows of cells, and connecting said sense output terminal interconnect links to selected first and second sense nodes.   
     
     
       6. A method according to claim 5, wherein said cell configuration includes a third cell boundary edge which intersects said first and second cell boundary edges, and wherein said first and second conductive control links are formed in step (b) so as to be parallel to one another and said third cell boundary edge. 
     
     
       7. A method according to claim 5, wherein said first and second controllable semiconductor switch devices comprise first and second field effect transistors, respectively, and wherein each of said first and second field effect transistors has one of its source and drain electrodes coupled to a respective one of said first and second sense nodes, and the other of its source and drain electrodes coupled to a respective one of said first and second output nodes, and wherein step (d) comprises forming said first control node connection link so as to be connected to the gate electrode of said first field effect transistor, and forming said second control node connection link so as to be connected to the gate electrode of said second field effect transistor. 
     
     
       8. A method of manufacture of a semiconductor circuit cell architecture, in accordance with a cell topography that facilitates placement of respective cells in abutting relationship in a multiple cell layout, and testing of said respective cells, prior to routing interconnect material to conductive links within and to selected nodes among said respective cells, said method of manufacture comprising the steps of: (a) forming a semiconductor circuit at a first physical location of a generally rectangular physical topography geometry of a semiconductor cell, said semiconductor circuit having an input terminal to which an input signal is applied, an output terminal from which an output signal is derived, a sense node for monitoring an operation of said semiconductor circuit, and a sense output terminal;   (b) forming a controllable semiconductor switching device at a second physical location of said generally rectangular physical topography geometry of said semiconductor cell, said controllable semiconductor switching device being controllably operative to couple said sense node to said sense output terminal, and wherein said controllable semiconductor switching device has an output node, an input node, and a control node, and wherein said control node, in response to receiving a control signal supplied by a test circuit, controllably causes said controllable semiconductor switching device to provide a conductive path between said Sense node and said sense output terminal;   (c) physically forming a conductive control link which extends across said semiconductor cell, so as to afford physical placement of respective cells in cell-to-cell mutually abutting relationship, in order to effectively form a continuous physical run of said conductive control link through mutually abutting cells;   (d) prior to forming control node connection links that serve to selectively electrically interconnect control nodes of controllable switching devices of semiconductor cells that are placed so as to abut one another and selected ones of conductive control links of abutting semiconductor cells, and prior to routing interconnect material among respective ones of a plurality of abutting semiconductor cells, placing a plurality of abutting semiconductor cells in abutting relationship such that sense nodes of abutting semiconductor cells are disposed adjacent to one another for interconnection to a common output terminal link; and   (e) physically forming a control node connection link so as to electrically interconnect said control node of said controllable semiconductor switching device and said conductive control link, and physically routing output terminal interconnect links among selected abutting semiconductor cells, and connecting said output terminal interconnect links to selected sense nodes, such that controllable semiconductor switching devices, whose sense nodes are connected to the same output terminal interconnect link, are connected to different control node connection links.   
     
     
       9. A method according to claim 8, wherein said semiconductor circuit cell architecture has a cell boundary edge which intersects opposite cell boundary edges, and wherein step (c) comprises physically forming said conductive control link to be parallel to said cell boundary edge. 
     
     
       10. A method according to claim 8, wherein step (c) comprises physically forming said control link in proximity with said controllable semiconductor switch device. 
     
     
       11. A method according to claim 8, wherein said controllable semiconductor switch device comprises a field effect transistor, having one of source and drain electrodes thereof coupled to said sense node, and the other of source and drain electrodes thereof coupled to said output node, and wherein step (e) comprises forming said control node connection link so as to be electrically connected to the gate electrode of said field effect transistor. 
     
     
       12. A method according to claim 8, wherein said sense output terminal intersects one of said opposite cell boundary edges. 
     
     
       13. A method of manufacture of a multi-cell integrated circuit architecture, in accordance with a cell topography that facilitates placement of respective cells in abutting relationship in a multiple cell layout, and testing of said respective cells prior to routing interconnect material to conductive links within and to selected nodes among said respective cells, said method of manufacture comprising the steps of: (a) forming a matrix of rows and columns of semiconductor circuit cells in a semiconductor substrate, such that a respective row of cells contains cells arranged in mutual abutment with one another, and wherein each of plural ones of said cells have a standard cell configuration that comprises: (i) a generally rectangular semiconductor topography geometry and including a semiconductor circuit disposed at a first physical location thereof, said semiconductor circuit having an input terminal to which an input signal is applied, an output terminal from which an output signal is derived, a sense node for monitoring an operational of said semiconductor circuit, and a sense output terminal;   (ii) a controllable semiconductor switching device, located at a second physical location of said generally rectangular semiconductor topography geometry, and which is controllably operative to couple said sense node to said sense output terminal, said controllable semiconductor switching device having an output node, an input node, and a control node, and wherein said control node, in response to receiving a control signal supplied by a test circuit, controllably causes said controllable semiconductor switching device to provide a conductive path between said sense node and said sense output terminal;     (b) forming a conductive control link extending across said standard cell so as to afford placement of respective cells in said mutual abutting relationship, in order to effectively form a continuous run of said conductive control link through mutually abutting cells;   (c) prior to forming control node connection links that serve to selectively electrically interconnect control nodes of controllable switching devices of cells that are placed to abut one another and selected ones of conductive control links of said abutting cells, and prior to routing interconnect material among respective ones of a plurality of said semiconductor cells, placing a plurality of said semiconductor cells in abutting relationship such that sense nodes of abutting cells are disposed adjacent to one another so as to be interconnectable to a common output terminal link; and   (d) forming a control node connection link to interconnect said control node of said controllable semiconductor switching device and said control connective link, such that respectively different controllable semiconductor switching devices, whose sense nodes are connected to the same terminal interconnect link are connected to different control node connection links; and   (e) selectively routing sense output terminal interconnection links among the output terminals of cells of adjacent rows of cells, and connecting said sense output terminal interconnect links to selected sense nodes.   
     
     
       14. A method according to claim 13, wherein said cell configuration includes a cell boundary edge which intersects opposite cell boundary edges, and wherein said conductive control link is formed in step (b) so as to be parallel to said cell boundary edge. 
     
     
       15. A method according to claim 13, wherein said controllable semiconductor switch device comprises a field effect transistor having one of its source and drain electrodes coupled to said sense node, and the other of its source and drain electrodes coupled to said output node, and wherein step (d) comprises forming said control node connection link so as to be connected to the gate electrode of said field effect transistor. 
     
     
       16. A method according to claim 13, wherein said sense output terminal intersects one of said opposite cell boundary edges, thereby allowing sense output terminals of cells of adjacent rows of a matrix of cells to be electrically interconnected by a conductive layer therebetween physically extending in a direction generally parallel to mutual abutment of cells of a respective row of cells.