Direct digital synthesizer capable of reducing spurious noise components

Abstract

A direct digital synthesizer (DDS) 3 comprises a phase accumulator for generating phase data in response to frequency data, periodic signal converters for generating a sine signal and a cosine signal in response to the upper bits of the phase data, phase error signal generating means for generating a phase error signal in response to the lower bits of the phase data, a multiplier for multiplying the cosine signal and the phase error signal to produce a spurious cancel signal, and a subtracter 35 for subtracting the spurious cancel signal from the sine signal, thereby obtaining a resultant sine signal free from spurious noise.

What is claimed is: 
     
       1. A direct digital synthesizer comprising: means accumulating frequency data to produce phase data;   means responsive to said phase data from said accumulating means producing predetermined trigonometric function data;   digital-to-analog converting means converting said predetermined trigonometric function data into an analog trigonometric function signal;   means responsive to said phase data from said accumulating means producing an analog spurious canceling signal; and   means combining said analog trigonometric function signal and said analog spurious canceling signal to produce a resultant analog synthesized signal.   
     
     
       2. A direct digital synthesizer as claimed in claim 1, wherein said predetermined trigonometric function data producing means produces said predetermined trigonometric function data in response to significant bits of said phase data, said spurious canceling signal producing means includes means for producing phase-advanced trigonometric function data in response to said significant bits of said phase data, said phase-advanced trigonometric function data being phase-advanced relative to said predetermined trigonometric function data, means producing phase error data in response to less significant bits of said phase data, digital-to-analog converting means converting said phase-advanced trigonometric function data into an analog phase-advance trigonometric function signal, and digital-to-analog converting means converting said error data into an analog phase error signal, and means multiplying said analog phase-advanced trigonometric function signal and said analog phase error signal to produce said analog spurious canceling signal.   
     
     
       3. A direct digital synthesizer comprising: phase accumulator means accumulating frequency data to produce phase data;   a first phase-to-analog converter for generating sine amplitude data corresponding to the value of said significant bits;   a first digital-to-analog converter for converting said sine amplitude data into an analog sine signal;   a second digital-to-analog converter for converting said cosine amplitude data into an analog cosine signal;   an error data converter for converting less significant bits of said phase data into phase error data;   a third digital-to-analog converter for converting said phase error data into an analog phase error signal;   a multiplier for multiplying said analog cosine signal and said analog phase error signal to produce an analog spurious cancel signal; and   a subtracter for subtracting said analog spurious cancel signal from said analog sine signal to produce a resultant analog synthesized signal.   
     
     
       4. A direct digital synthesizer comprising: phase accumulator means accumulating frequency data to produce phase data;   phase-to-sine signal converting means generating a sine signal in response to significant bits of said phase data, said phase-to-sine signal converting means including a first phase-to-amplitude converter for generating sine amplitude data corresponding to the value of said significant bits, and a second converter for converting said sine amplitude data into said sine signal;   phase-to-cosine signal converting means generating a cosine signal, which is advanced in phase by 90 degrees relative to said sine signal, in response to said significant bits, said phase-to-cosine signal converting means including a second phase-to-amplitude converter for generating cosine amplitude data corresponding to the value of said significant bits, and a third converter for converting said cosine amplitude data into said cosine signal;   a first converter for converting less significant bits of said phase data into a phase error signal;   a multiplier for multiplying said cosine signal and said phase error signal to produce a spurious cancel signal;   a subtracter for subtracting said spurious cancel signal from said sine signal to produce a resultant synthesized signal;   a first timing adjusting circuit for causing said cosine signal and said phase error signal to arrive at input terminals of said multiplier substantially at the same timing;   a first level adjusting circuit for confining signal levels of said cosine signal and said phase error signal on said input terminals of multiplier in a predetermined range necessary for said multiplier;   a second timing adjusting signal for causing a spurious component of said sine signal and said spurious cancel signal to arrive at input terminals of said subtracter at substantially the same time; and   a second level adjusting circuit for setting said sine signal and said spurious cancel signal on said input terminals of said subtracter at respective signal levels which minimize said spurious component of said resultant synthesized signal.   
     
     
       5. A direct digital synthesizer comprising: phase accumulator means accumulating frequency data to produce phase data;   phase-to-sine signal converting means generating a sine signal in response to significant bits of said phase data;   phase-to-cosine signal converting means generating a cosine signal, which is advanced in phase by 90 degrees relative to said sine signal, in response to said significant bits;   a first converter for converting less significant bits of said phase data into a phase error signal;   a multiplier for multiplying said cosine signal and said phase error signal to produce a spurious cancel signal;   a subtracter for subtracting said spurious cancel signal from said sine signal to produce a resultant synthesized signal; and   zero-cross detecting means generating, on detecting a zero-crossing point of said resultant synthesized signal, an iterative signal having a period corresponding to an interval between detected zero-crossing points.   
     
     
       6. A digital frequency synthesizer as claimed in claim 5, wherein said zero-cross detecting means comprises a low pass filter for filtering out a DC component contained in said resultant synthesized signal, and a comparator for comparing said resultant synthesized signal and said DC component to thereby produce said iterative signal.