Apparatus for determining the direction of signal/data flow on CSI bus for converting between single ended and differential type signals

Abstract

The disclosed invention is an apparatus in a computer peripheral device for determining the direction of signal flow and data flow on a SCSI bus, which apparatus comprises a time delay means responsive to status signals of the SCSI bus. The time delay means generates a signal that defines an arbitration selection period of time for determining control of the SCSI bus. The apparatus further includes a first circuit means responsive to the arbitration selection signal and status signals of the SCSI bus. The first circuit means generates a plurality of signals that determine whether the peripheral device is an initiator of signals to be transmitted on the bus or is a target for receipt of signals present on the bus. Moreover, the apparatus includes a second circuit means that is responsive to the plurality of signals generated by the first circuit means and status signals of the bus. The second circuit means generates a pair of signals indicative of the direction of data and signal flow on the SCSI bus.

What is claimed is: 
     
       1. An apparatus in a computer peripheral device for determining the direction of signal and data flow using SCSI bus protocol including BUS BUSY (BSY), COMMAND or DATA (C/D), MESSAGE (MSG), INPUT or OUTPUT (I/O) and SELECT DEVICE (SEL) phases, said apparatus comprising: a. time delay means responsive to said BSY and SEL phases, said time delay means being disposed for generating an arbitration selection signal defining a period of time to determine control of said SCSI bus;   b. first circuit means responsive to said arbitration selection signal and said BSY, SEL and I/O phases, said first circuit means being disposed for generating a plurality of signals that determine whether said peripheral device is an initiator of signals to be transmitted on said SCSI bus or a target for receipt of signals present on said SCSI bus;   c. second circuit means responsive to said plurality of signals generated by said first circuit means and said BSY, SEL, I/O, MSG and C/D phases, said second circuit means being disposed for generating a pair of signals indicative of the direction of data and signal flow on said SCSI bus and further including a first gating network having inputs coupled to said MSG, C/D and I/O phases and having outputs coupled to a first set of inputs of a first pair of AND gates, respectively, and a second set of inputs coupled to an output of a latch means set and reset as a function of said BSY and SEL phases, wherein an output of a first of said first pair of AND gates is a signal indicative of said peripheral device being an initiator and an output of a second of said pair of AND gates is a signal indicative of said peripheral device being a target device, and a second gating network having a first set of inputs coupled to said output of said first of said first pair of AND gates, a second set of inputs coupled to said output of said second of said pair of AND gates and a third set of inputs coupled to outputs of said first circuit means, a first output of said second gating network providing a signal for converting from single-ended to differential signal format thereby forcing signal and data flow in a first direction, and a second output of said second gating network providing a signal for converting from differential to single-ended signal format thereby forcing signal and data flow in a second direction.   
     
     
       2. An apparatus as in claim 1 wherein said time delay means includes a counter means that is enabled by status signals on said SCSI bus. 
     
     
       3. An apparatus as in claim 2 further including latch means set as a function of the count in said counter means and reset as a function of status signals on said SCSI bus, the output of said latch means being said arbitration selection signal. 
     
     
       4. An apparatus as in claim 1 wherein said first circuit means includes a pair of gating means having inputs disposed for receiving said arbitration selection signal and status signals of said SCSI bus and outputs coupled to inputs of a pair of latch means, respectively, said gating means being disposed for setting said latch means in response to said arbitration selection signal as a function of status of said SCSI bus. 
     
     
       5. An apparatus as in claim 4 wherein an output of a first of said pair of latch means is a signal indicative of said peripheral device being selected for control of said SCSI bus, thereby being an initiator device for transmitting signals. 
     
     
       6. An apparatus as in claim 5 including AND gating means having a first set of inputs coupled to the output of said first of said pair of latch means, a second set of inputs disposed for receiving signals indicative of the direction of signal flow on said SCSI bus and outputs coupled to inputs of a second pair of latch means, said AND gating means being disposed for setting said second pair of latch means during a select mode of operation. 
     
     
       7. An apparatus as in claim 4 wherein an output of a second of said pair of latch means is a signal indicative of said peripheral device being selected to receive signals from said SCSI bus, thereby being a target device for receipt of signals. 
     
     
       8. An apparatus as in claim 7 further including AND gating means having a first set of inputs coupled to the output of said second of said pair of latch means, a second set of inputs disposed for receiving signals indicative of the direction of signal flow on said SCSI bus and outputs coupled to inputs of a third pair of latch means, said AND gating means being disposed for setting said third set of latch means as a function of a reselect mode of operation. 
     
     
       9. An apparatus as in claim 1 wherein said second circuit means includes a latch means set when said SCSI bus is not busy and having an output thereof. 
     
     
       10. An apparatus in a computer peripheral device for determining the direction of signal and data flow using SCSI bus protocol including BUS BUSY (BSY), COMMAND or DATA (C/D), MESSAGE (MSG), INPUT or OUTPUT (I/O) and SELECT DEVICE (SEL) phases, said apparatus comprising: a. time delay means responsive to said BSY and SEL phases, said time delay means being disposed for generating an arbitration selection signal defining a period of time to determine control of said SCSI bus, said time delay means further including a counter means that is enabled by status signals on said SCSI bus;   b. first circuit means responsive to said arbitration selection signal and said BSY, SEL and I/O phases, said first circuit means being disposed for generating a plurality of signals that determine whether said peripheral device is an initiator of signals to be transmitted on said SCSI bus or a target for receipt of signals present on said SCSI bus, said first circuit means further including a pair of gating means having inputs disposed for receiving said arbitration selection signal and status signals of said SCSI bus and outputs coupled to inputs of a pair of latch means, respectively;   c. second circuit means responsive to said plurality of signals generated by said first circuit means and said BSY, SEL, I/O, MSG and C/D phases, said second circuit means being disposed for generating a pair of signals indicative of the direction of data and signal flow on said SCSI bus and further including a first gating network having inputs coupled to said MSG, C/D and I/O phases and having outputs coupled to a first set of inputs of a first pair of AND gates, respectively, and a second set of inputs coupled to an output of a latch means set and reset as a function of said BSY and SEL phases, wherein an output of a first of said first pair of AND gates is a signal indicative of said peripheral device being an initiator and an output of a second of said pair of AND gates is a signal indicative of said peripheral device being a target device, and a second gating network having a first set of inputs coupled to said output of said first of said first pair of AND gates, a second set of inputs coupled to said output of said second of said pair of AND gates and a third set of inputs coupled to outputs of said first circuit means, a first output of said second gating network providing a signal for converting from single-ended to differential signal format thereby forcing signal and data flow in a first direction, and a second output of said second gating network providing a signal for converting from differential to single-ended signal format thereby forcing signal and data flow in a second direction.   
     
     
       11. An apparatus as in claim 10 further including latch means set as a function of the count in said counter means and reset as a function of status signals on said SCSI bus, the output of said latch means being said arbitration selection signal. 
     
     
       12. An apparatus as in claim 11 wherein an output of a first of said pair of latch means is a signal indicative of said peripheral device being selected for control of said SCSI bus,thereby being an initiator device for transmitting signals. 
     
     
       13. An apparatus as in claim 12 including AND gating means having a first set of inputs coupled to the output of said first of said pair of latch means, a second set of inputs disposed for receiving signals indicative of the direction of signal flow on said SCSI bus and outputs coupled to inputs of a second pair of latch means, said AND gating means being disposed for setting said second pair of latch means during a select mode of operation. 
     
     
       14. An apparatus as in claim 10 wherein an output of a second of said pair of latch means is a signal indicative of said peripheral device being selected to receive signals from said SCSI bus, thereby being a target device for receipt of signals. 
     
     
       15. An apparatus as in claim 14 further including AND gating means having a first set of inputs coupled to the output of said second of said pair of latch means, a second set of inputs disposed for receiving signals indicative of the direction of signal flow on said SCSI bus and outputs coupled to inputs of a third pair of latch means, said AND gating means being disposed for setting said third set of latch means as a function of a reselect mode of operation. 
     
     
       16. An apparatus in a computer peripheral device for determining the direction of signal and data flow using SCSI bus protocol including BUS BUSY (BSY), COMMAND or DATA (C/D), MESSAGE (MSG), INPUT or OUTPUT (I/O) and SELECT DEVICE (SEL) phases, said apparatus comprising: a. a time delay means responsive to said BSY and SEL phases, said time delay means being disposed for generating an arbitration selection signal defining a period of time to determine control of said SCSI bus, said time delay means further including a counter means that is enabled by status signals on said SCSI bus and a latch means set as a function of the count in said counter means and reset as a function of status signals on said SCSI bus, the output of said latch means being said arbitration selection signal;   b. first circuit means responsive to said arbitration selection signal and said BSY, SEL and I/O phases, said first circuit means being disposed for generating a plurality of signals that determine whether said peripheral device is an initiator of signals to be transmitted on said SCSI bus or a target for receipt of signals present on said SCSI bus, said first circuit means further including a pair of gating means having inputs disposed for receiving said arbitration selection signal and status signals of said SCSI bus and outputs coupled to inputs of a pair of latch means, respectively, wherein an output of a first of said pair of latch means is a signal indicative of said peripheral device being selected for control of said SCSI bus, thereby being an initiator device for transmitting signals and AND gating means having a first set of inputs coupled to the output of said first of said pair of latch means, a second set of inputs disposed for receiving signals indicative of the direction of signal flow on said SCSI bus and outputs coupled to inputs of a second pair of latch means;   c. second circuit means responsive to said plurality of signals generated by said first circuit means and said BSY, SEL, I/O, MSG and C/D phases, said second circuit means being disposed for generating a pair of signals indicative of the direction of data and signal flow on said SCSI bus, and further including a first gating network having inputs coupled to said MSG, C/D and I/O phases and having outputs coupled to a first set of inputs of a first pair of   AND gates, respectively, and a second set of inputs coupled to an output of a latch means set and reset as a function of said BSY and SEL phases, wherein an output of a first of said first pair of AND gates is a signal indicative of said peripheral device being an initiator and an output of a second of said pair of AND gates is a signal indicative of said peripheral device being a target device, and a second gating network having a first set of inputs coupled to said output of said first of said first pair of AND gates, a second set of inputs coupled to said output of said second of said pair of AND gates and a third set of inputs coupled to outputs of said first circuit means, a first output of said second gating network providing a signal for converting from single-ended to differential signal format thereby forcing signal and data flow in a first direction, and a second output of said second gating network providing a signal for converting from differential to single-ended signal format thereby forcing signal and data flow in a second direction.   
     
     
       17. An apparatus as in claim 16 wherein said second circuit means further includes a first gating network having inputs coupled to status signals of said SCSI bus and having outputs coupled to a first set of inputs of a first pair of AND gates, respectively, and a second set of inputs coupled to an output of a latch set and reset as a function of status of said SCSI bus, wherein the output of a first of said first pair of AND gates is a signal indicative of said peripheral device being an initiator device and the output of a second of said first pair of AND gates is a signal indicative of said peripheral device being a target device.