Device for switching high speed protocol units, and corresponding switching procedure

Abstract

A high speed switching device among a multiplicity of processing modules, for enabling data exchanges of data organized into protocol units, includes a multiplicity of switching interface modules each including an FIFO input memory connected to an input bus and an FIFO output bus, a switching module capable of connecting each of the input buses with each of the output buses, and an arbitration and command module for commanding the switching effected by the switching module. The arbitration and command module commands switching once the destination switching interface module has at least one free space.

We claim: 
     
       1. A high speed switching device among a multiplicity of processing modules for enabling exchanges of data organized into protocol units, comprising: a multiplicity of switching interface modules each including a FIFO input memory connected to an input bus and a FIFO output memory connected to an output bus, each of the memories including at least one space which is able to contain one of the protocol units, and data exchange controlling means, each of the switching interface modules being capable of being connected to one of the processing modules, in such a way that the processing module may inscribe data in the input memory and read data in the said output memory;   a switching module, capable of connecting each of the input buses with each of the output buses;   an arbitration and command module commanding switching effected by the switching module, as a function of requests received from the data exchange controlling means in the switching interface modules, and the arbitration and command module delivering corresponding connection commands to the date exchange controlling means once switching has been effected;   the data exchange controlling means from one of the switching interface modules transmitting a request, which indicates at least one destination switching interface module, to the arbitration and command module once the protocol unit has been inscribed in the input memory; and   the arbitration and command module commanding a corresponding switching once the output memory of the destination switching interface module has at least one free place.   
     
     
       2. A high speed switching device according to claim 1, wherein each of the switching interface modules is linked to the arbitration and command module by: an input connection bus, by which the arbitration and command module indicates to a switching interface module which has transmitted a transmission request that a corresponding switching has been effected;   an output connection bus, by which the arbitration and command module indicates to a destination switching interface module that is going to receive a protocol unit;   a release bus, by which the destination switching interface module indicates to the arbitration and command module that the protocol unit has been received;   a requests bus, by which a switching interface module transmits a request, including an address of the destination switching interface module, to the arbitration and command module.   
     
     
       3. A high speed switching device according to claim 2, wherein the requests bus includes a single wire, on which binary elements which make up the request are transmitted in series. 
     
     
       4. A high speed switching device according to claim 1, wherein the arbitration and command module implements a processing pipeline, arbitration of switching a current protocol unit being effected simultaneously to transfer of a preceding protocol unit. 
     
     
       5. A high speed switching device according to claim 4, further comprising time means for dividing time into switching cycles, duration of a cycle corresponding to duration of a protocol unit of predetermined size, the arbitration and command module includes: means for receiving requests;   means for arbitrating connections for a following cycle;   means for transmitting switching commands for the following cycle to the switching module; and   means for validating switching commands.   
     
     
       6. A high speed switching device according to claim 1, wherein the input buses and output buses are eight, sixteen or thirty-two bit parallel buses. 
     
     
       7. A high speed switching device according to claim 1, wherein each of the processing modules is implanted on a separate switching interface support card, and the switching module is implanted on a switching support card, and the switching interface support cards and the switching support cards are grouped in such a way that a distance between each of the switching interface support cards and the switching support card are substantially identical. 
     
     
       8. A high speed switching device according to claim 7, wherein the switching interface support cards are substantially perpendicular to each other, and the switching interface support cards are substantially perpendicular to the switching interface support cards. 
     
     
       9. A method of high speed switching among a multiplicity of processing modules, for enabling exchange of data organized into protocol units, comprising the steps of: writing a protocol unit to be transmitted, by a transmitting processing module, into a FIFO input memory of an initial switching interface module linked to the transmitting processing module;   transmitting a connection request which specifies an address of a destination processing module to a single arbitration and command module;   when the destination processing module is available, commanding the arbitration and command module of a switching module, in such a way that the switching module connects an input bus connected to the FIFO input memory to an output bus connected to a FIFO output memory of a second switching interface module which is linked to the destination processing module;   transmitting a transfer command to the transmitting processing module and destination processing module by the arbitration and command module;   transferring the protocol unit in the FIFO output memory of the second switching interface module; and   transmitting release information by the second switching interface module to the arbitration and command module, once transfer has been effected and when there is sufficient space in the FIFO output memory of the second switching interface module for at least one protocol unit.   
     
     
       10. A method of high speed switching according to claim 9, wherein the connection request in the step of transmitting the connection request is effected in series, on a single wire requests bus. 
     
     
       11. A method of high speed switching according to claim 9, further comprising a step of implementing a pipeline processing procedure, arbitration of switching of a protocol unit being effected simultaneously to transfer of a preceding protocol unit. 
     
     
       12. A method of high speed switching according to claim 11, wherein time is divided into switching cycles, duration of a cycle corresponding to duration of a segment corresponding to a protocol unit of predetermined size. 
     
     
       13. A method of high speed switching according to claim 12, wherein each segment carries information indicating whether or not said each segment is a last segment in a series of segments forming a protocol unit, a connection is systematically maintained for a following cycle when a current segment being transferred is not the last segment, and release information is transmitted when the last segment has been received and when the output memory has sufficient space to receive a new protocol unit.