Testing buffer/register

Abstract

A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.

What is claimed is: 
     
       1. An integrated circuit operable in test and normal modes, comprising: input circuitry for receiving input data;   output circuitry for transmitting output data;   application logic circuitry coupled to said input circuitry and said output circuitry for performing a function on said input data and producing said output data;   input test cells coupled to said input circuitry, for performing internally controlled test operations while said integrated circuit is in said test mode;   output test cells coupled to said output circuitry, for performing internally controlled test operations while said integrated circuit is in said test mode; and   test control circuitry coupled to said input and output test cells to communicate serial data to and from said integrated circuit, said serial data communicated to said test cells by said test control circuitry to setup said input and output test cells for a selected internally controlled test operation while said integrated circuit is in said normal node, said test control circuitry having control outputs that are coupled to said input and output test cells and which control execution of said internally controlled test operation by said input and output test cells after said setup is complete, said test control circuitry communicating serial data from said integrated circuit by serially unloading test results from said input and output test cells after said internally controlled test operation has completed and said integrated circuit returns to said normal mode.   
     
     
       2. The integrated circuit of claim 1 wherein said application logic circuitry comprises at least a combinational logic circuit. 
     
     
       3. The integrated circuit of claim 2 wherein said operation of communicating serial data from said integrated circuit to unload test results from said test input test cells and output test cells does not change the stored test results in said input test cells and said output test cells. 
     
     
       4. The integrated circuit of claim 1 wherein said application logic circuitry comprises at least a sequential logic circuit. 
     
     
       5. The integrated circuit of claim 1 wherein said input test cells are coupled between said input circuitry and said application logic circuitry. 
     
     
       6. The integrated circuit of claim 1 wherein said output test cells are coupled between said application logic circuitry and said output circuitry. 
     
     
       7. The integrated circuit of claim 1 wherein said input test cells comprise circuitry to receive and store the input data received by said input circuitry in response to said control outputs from said test control circuitry. 
     
     
       8. The integrated circuit of claim 1 wherein said output test cells comprise circuitry to receive and store the output data from said application logic circuitry in response to said control outputs from said test control circuitry. 
     
     
       9. The integrated circuit of claim 1 wherein said input test cells comprise circuitry to perform parallel signature analysis on said input data in response to said control outputs from said test control circuitry. 
     
     
       10. The integrated circuit of claim 9 wherein said input test cells further comprise circuitry to mask selected signals of said input data from said parallel signature analysis operation. 
     
     
       11. The integrated circuit of claim 9 wherein said input test cells comprise programmable polynomial feedback logic circuitry. 
     
     
       12. The integrated circuit of claim 1 wherein said output test cells perform parallel signature analysis on data output by said application logic circuitry in response to said control outputs from said test control circuitry, and wherein at least some of said output test cells further comprise masking logic circuitry to mask selected signals of said output data from said parallel signature analysis operation responsive to said control outputs. 
     
     
       13. The integrated circuit of claim 1 wherein said output test cells selectively perform pseudorandom pattern generation for generating said output data and selectively output said pseudorandom patterns on a selected group of said output signals in response to said control outputs from said test control circuitry. 
     
     
       14. The integrated circuit of claim 13 wherein said output test cells further comprise programmable polynomial feedback logic circuitry. 
     
     
       15. The integrated circuit of claim 1 wherein said output test cells comprise circuitry to selectively output binary counting patterns as said output data on a selected group of said output data signals in response to said control outputs from said test control circuitry. 
     
     
       16. The integrated circuit of claim 1 wherein said output test cells comprise circuitry to selectively output toggle patterns as said output data on a selected group of said output data signals in response to said control outputs from said test control circuitry. 
     
     
       17. The integrated circuit of claim 1 wherein said input test cells and said output test cells perform tests simultaneously when said integrated circuit is in said test mode, so that said input data is received by said input test cells as test data while said output test cells output test data as said output data in response to said control outputs from said test control circuitry. 
     
     
       18. The integrated circuit of claim 17 wherein said input test cells receive data from selected signals of said input data and said output test cells output test data to selected signals of said output data. 
     
     
       19. The integrated circuit of claim 17 wherein said input test cells perform signature analysis on said input data while said output test cells simultaneously output pseudorandom patterns as said output data. 
     
     
       20. The integrated circuit of claim 17 wherein said input test cells perform signature analysis on said input data while said output test cells simultaneously output binary counting patterns as said output data. 
     
     
       21. The integrated circuit of claim 17 wherein said input test cells perform signature analysis on said input data while said output test cells simultaneously output toggle patterns as said output data. 
     
     
       22. The integrated circuit of claim 17 wherein, while said integrated circuit is in said test mode: said output test cells transmit test data as outputs on a first clock edge;   said input test cells store input data as test data on the next clock edge; and   said input test cells subsequently serially output said stored input data as test data responsive to said test control circuitry, said input test cells and said output test cells being prevented from storing and transmitting additional test data until said serial output is completed.   
     
     
       23. The integrated circuit of claim 17 wherein said data outputs of said integrated circuit are each placed in a tristate condition while serial data is shifted through a scan path in the test control circuitry, said scan path comprising a single flip flop. 
     
     
       24. The integrated circuit of claim 17 wherein said data outputs of said integrated circuit are each placed in predetermined states while serial data is shifted through a scan path in the test control circuitry, said scan path comprising a single flip flop.