CMOS level conversion circuit with input protection

Abstract

The current paths of the P-channel transistor, P-channel transistor, and N-channel transistor are connected in series between the power source V DD and the ground. The inverter circuit is constituted by the transistors. The node of the inverter circuit is connected to an end of the current path of the N-channel transistor. Another end of the current path of the N-channel transistor is connected to the input node. The transistors are of the enhancement type. If the electric potential higher than the power source V DD is supplied to the input node, the voltage of the node is lower than that of the power source V DD by the threshold voltage (V THN ) and the transistors are protected from destruction.

What is claimed is: 
     
       1. A level conversion circuit having only field effect transistors of the enhancement type, comprising: a first transistor of a first conductive type having a gate and a current path, the gate of the first transistor of the first conductive type being connected to a signal input terminal and one end of the current path being connected to a first electric potential;   a second transistor of the first conductive type having a gate and a current path, one end of the current path of the second transistor of the first conductive type being connected to another end of the current path of the first transistor and another end of the current path of the second transistor of the first conductive type being connected to an output terminal;   a first transistor of a second conductive type having a gate and a current path, one end of the current path of the first transistor of the second conductive type being connected to the output terminal and another end thereof being connected to a second electric potential; and   a second transistor of the second conductive type having a gate and a current path, the gate of the second transistor of the second conductive type being connected to the first electric potential, one end of the current path being connected to the signal input terminal, another end thereof being directly connected to the gate of the second transistor of the first conductive type and the gate of the first transistor of the second conductive type,   wherein a potential of said another end of said second transistor of said second conductive type differs from a potential of said one end of said second transistor of said second conductive type.   
     
     
       2. The circuit according to claim 1, wherein the voltage between the gate and source, between the gate and drain, and between the drain and the source in each of the first transistor of the first conductive type, the second transistor of the first conductive type, the first transistor of the second conductive type, and the second transistor of the second conductive type is predetermined to be under the first electric potential. 
     
     
       3. The circuit according to claim 1, wherein the sum of the threshold voltage of the second transistor of the second conductive type and that of the first transistor of the second conductive type is predetermined to be under the first electric potential. 
     
     
       4. The circuit according to claim 1, wherein the first and second transistors of the first conductive type are P-channel transistors, and the first and second transistors of the second conductive are N-channel transistors. 
     
     
       5. A circuit according to claim 1, wherein said potential of said another end of said second transistor of the second conductive type is lower than a potential of the one end of said second transistor of the second conductive type. 
     
     
       6. A level conversion circuit having only field effect transistors of the enhancement type, comprising: a first transistor of a first conductive type having a gate and a current path, the gate of the first transistor of the first conductive type being connected to a signal input terminal and one end of the current path being connected to a first electric potential;   a second transistor of the first conductive type having a gate and a current path, one end of the current path of the second transistor of the first conductive type being connected to another end of the current path of the first transistor and another end of the current path of the second transistor of the first conductive type being connected to an output terminal;   a first transistor of a second conductive type having a gate and a current path, one end of the current path of the first transistor of the second conductive type being connected to the output terminal and another end thereof being connected to a second electric potential;   a second transistor of the second conductive type having a gate and a current path, the gate of the second transistor in the second conductive type being connected to the first electric potential, one end of the current path being connected to the signal input terminal, another end thereof being connected to the gate of the second transistor of the first conductive type and the gate of the first transistor of the second conductive type;   a third transistor of the second conductive type having a gate and a current path, the gate and one end of the current path of the third transistor of the second conductive type being connected to the first electric potential and another end of the current path of the third transistor of the second conductive type being connected to said another end of the current path of the first transistor of the first conductive type; and   a third transistor of the first conductive type having a gate and a current path, wherein the gate and one end of the current path of the third transistor of the first conductive type are connected to the first electric potential, and another end of the current path is connected to said another end of the current path of the second transistor of the second conductive type.   
     
     
       7. The circuit according to claim 6, wherein the voltage between the gate and source, between the gate and drain, and between the drain and the source in each of the first transistor of the first conductive type, the second transistor of the first conductive type, the first transistor of the second conductive type, and the second transistor of the second conductive type is predetermined to be under the first electric potential. 
     
     
       8. The circuit according to claim 6, wherein the sum of the threshold voltage of the second transistor of the second conductive type and that of the first transistor of the second conductive type is predetermined to be under the first electric potential. 
     
     
       9. A level conversion circuit comprising: a first P-channel transistor having a gate and a current path, the gate of the first P-channel transistor being connected to a signal input terminal and one end of the current path being connected to a first electric potential;   a second P-channel transistor having a gate and a current path, one end of the current path of the second P-channel transistor being connected to another end of the current path of the first P-channel transistor and another end of the current path of the second P-channel transistor connected to an output terminal;   a first N-channel transistor having a gate and a current path, one end of the current path of the first N-channel transistor being connected to the output terminal and another end thereof being connected to a second electric potential; and   a second N-channel transistor having a gate and a current path, the gate of the second N-channel transistor being connected to the first electric potential, one end of the current path being connected to the signal input terminal, another end thereof being directly connected to the gate of the second P-channel transistor and the gate of the first N-channel transistor,   wherein a potential of said another end of said second N-channel transistor is lower than a potential of said one end of said second N-channel transistor.   
     
     
       10. The circuit according to claim 9, wherein the voltage between the gate and source, between the gate and drain, and between the drain and the source in each of the first P-channel transistor, the second P-channel transistor, the first N-channel transistor, and the second N-channel transistor is predetermined to be under the first electric potential. 
     
     
       11. The circuit according to claim 9, wherein the sum of the threshold voltage of the second N-channel transistor and that of the first N-channel transistor is predetermined to be under the first electric potential. 
     
     
       12. The circuit according to claim 9, wherein the first P-channel transistor, the second P-channel transistor, the first N-channel transistor, and the second N-channel transistor are of the enhancement type. 
     
     
       13. A level conversion circuit comprising: a first transistor of a first conductive type having a gate and a current path, the gate of the first transistor of the first conductive type being connected to a signal input terminal and one end of the current path being connected to a first electric potential;   a second transistor of the first conductive type having a gate and a current path, one end of the current path of the second transistor of the first conductive type being connected to another end of the current path of the first transistor and another end of the current path of the second transistor of the first conductive type being connected to an output terminal;   a first transistor of a second conductive type having a gate and a current path, one end of the current path of the first transistor of the second conductive type being connected to the output terminal and another end thereof being connected to a second electric potential;   a second transistor of the second conductive type having a gate and a current path, the gate of the second transistor of the second conductive type being connected to the first electric potential, one end of the current path being connected to the signal input terminal, another end thereof being connected to the gate of the second transistor of the first conductive type and the gate of the first transistor of the second conductive type;   a third transistor of the second conductive type having a gate and a current path, wherein the gate and one end of the current path of the third transistor of the second conductive type are connected to the first electric potential, and another end thereof is connected to said another end of the current path of the first transistor of the first conductive type; and   a third transistor of the first conductive type having a gate and a current path, wherein the gate and one end of the current path of the third transistor of the first conductive type are connected to the first electric potential and another end thereof is connected to said another end of the current path of the second transistor of the second conductive type.   
     
     
       14. The circuit according to claim 13, wherein the voltage between the gate and source, between the gate and drain, and between the drain and the source in each of the first transistor of the first conductive type, the second transistor of the first conductive type, the first transistor of the second conductive type, and the second transistor of the second conductive type is predetermined to be under the first electric potential. 
     
     
       15. The circuit according to claim 13, wherein the sum of the threshold voltage of the second transistor in of the second conductive type and that of the first transistor of the second conductive type is predetermined to be under the first electric potential. 
     
     
       16. The circuit according to claim 13, wherein the first transistor of the first conductive type, the second transistor of the first conductive type, the third transistor of the first conductive type, the first transistor of the second conductive type, the second transistor of the second conductive type, and the third transistor of the second conductive type are of the enhancement type.