Cascode array cell partitioning for a sense amplifier of a programmable logic device

Abstract

A sense amplifier for implementing a wide or multiple input NOR gate for receiving a product term of a group of array cells in a programable logic device (PLD). Array cells signals which are all normally received by the sense amplifier in a single product term input are instead connected to the sense amplifier in smaller groups of sub-product terms. Each smaller group of sub-product terms is then connected through a transistor cascode amplifier in the sense amplifier to form the single product term enabling a reduction of capacitance and an increase of output speed of the sense amplifier.

What is claimed is: 
     
       1. A programable array logic device comprising: a plurality of programable array cells;   a sense amplifier comprising: an amplifier having an amplifier input and an amplifier output;   a current source coupled to the amplifier input;   a product term A line coupled to a first plurality of array cells in the plurality of array cells;   a product term B line coupled to a second plurality of array cells in the plurality of array cells;   a first cascode having a current path coupled on a first end to the current source and the amplifier input and coupled on a second end to the product term A line, wherein a gate of the first cascode is supplied with a gate voltage to turn off the first cascode when a voltage on the product term A line is within a predetermined voltage range from a voltage on the amplifier input; and   a second cascode having a current path coupled on a first end to the current source and the amplifier input and coupled on a second end to the product term B line, wherein a gate of the second cascode is supplied with a gate voltage to turn off the first cascode when a voltage on the product term B line is within a predetermined voltage range from a voltage on the amplifier input; and   an output logic macro cell coupled to receive an output signal from the sense amplifier, the output logic macro cell being programable to select whether an output of the programable logic device will be registered or combinatorial.     
     
     
       2. The programmable array logic device of claim 1 further comprising: a first switching transistor having a gate coupled to the amplifier output and having a current path coupled on a first end to the product term A line;   a second switching transistor having a gate coupled to the amplifier output and having a current path coupled on a first end to the product term B line;   a first current sink coupled to a second end of the current path of the first switching transistor; and   a second current sink coupled to a second end of the current path of the second switching transistor.   
     
     
       3. The programable array logic device of claim 1 further comprising: a PTG current sink coupled to ground lines of the plurality of array cells;   a third cascode having a current path coupled on one end to the product term A line, and on a second end to the PTG current sink; and   a fourth cascode having a current path coupled on one end to the product term B line, and on a second end to the PTG current sink.