Symbol clock regeneration in digital signal receivers for recovering digital data buried in NTSC TV signals

Abstract

Digital data having a symbol rate that is a multiple of horizontal scan rate are buried in broadcast television signals. In a digital signal receiver the data are separated from composite video signal by quadrature video detection followed by comb filtering. The comb filtering is most economically realized by digital sampling at symbol rates. The regeneration of clocking signals at symbol rate, and at multiples of symbol rate where oversampling analog-to-digital conversion (ADC) techniques are employed, is done using a controlled oscillator with automatic frequency and phase control (AFPC) responding to the horizontal synchronizing pulses transmitted in the broadcast television signals. The horizontal synchronizing pulses are usually much larger than noise, so the controlled oscillator frequency and phase is rapidly adjusted following energization or channel change of the digital signal receiver. A fine adjustment of the phase of the oscillations from the controlled oscillator is made to minimize intersymbol error. This adjustment is made indirectly, by adjustably delaying the horizontal synchronizing pulses applied to the AFPC, so there is no discontinuity in the application of clocking signals to ADC circuitry and to comb filtering circuitry.

What is claimed is: 
     
       1. In a digital signal receiver receptive of a received signal including row synchronization signals occurring at a row rate and including analog signal representative of digital data having a symbol rate that is a multiple of row rate, clock regeneration circuitry comprising: a controlled oscillator for generating oscillations at a frequency that is controlled in response to an automatic-frequency-and-phase-control signal and that can be controlled to be a multiple of said symbol rate;   a frequency divider for dividing the frequency of the oscillations of said controlled oscillator by a factor equal to the number of said oscillations that are supposed to occur between corresponding points in consecutive row synchronization signals, to generate an automatic-frequency-and-phase-control feedback signal;   means, responsive to said received signal, for detecting the occurrence of said row synchronization signals in said received signal to generate line synchronization pulses;   a controlled delay line for delaying said line synchronization pulses in amount controlled by a delay control signal, thereby to provide delayed line synchronization pulses;   an automatic-frequency-and-phase-control detector for generating said automatic-frequency-and-phase-control signal responsive to differences in the respective frequencies and respective phases of said automatic-frequency-and-phase-control feedback signal and of said delayed line synchronization pulses, thereby completing a first feedback loop for applying automatic-frequency-and-phase-control signal to said controlled oscillator;   an analog-to-digital converter responsive to the oscillations of said controlled oscillator for sampling and digitizing said analog signal representative of digital data, thereby to generate at said symbol rate digitized signal samples representative of said digital data; and   means for determining sampling phase error in said digitized signal samples generated at said symbol rate, thereby to generate said delay control signal applied to said controlled delay line for completing a supplementary feedback loop for adjusting the sampling phase in said digitized signal samples to minimize inter-symbol interference.   
     
     
       2. Clock regeneration circuitry as set forth in claim 1; wherein said analog-to-digital converter is of an oversampling type, sampling said analog signal representative of digital data in accordance with a first clock signal supplied at an oversampling rate that is at least a two times multiple of said symbol rate, and supplying said digitized signal samples at said symbol rate in accordance with a second clock signal; and wherein said frequency divider includes: a zero-crossing detector for generating said first clock signal responsive to the oscillations of said controlled oscillator,   a first counter counting occurrences of said first clock signal for generating a first count signal and said second clock signal, each occurrence of said second clock signal corresponding to said first count signal attaining a value indicative of the prescribed number of samples per symbol period, said first count signal thereafter being returned to an initial value thereof;   a second counter counting occurrences of said second clock signal in each row or line period for generating a second count signal,   means detecting each time said second count signal reaches a value indicative of the prescribed number of symbols per row for generating a third clock signal applied to said automatic-frequency-and-phase-control detector as said automatic-frequency-and-phase-control feedback signal, and   means applying said third clock signal to said second counter for resetting said second count signal to an initial value thereof.   
     
     
       3. Clock regeneration circuitry as set forth in claim 2 further comprising: a third counter counting occurrences of said third clock signal in each row or line period for generating a third count signal and a fourth clock signal, respective occurrences of said fourth clock signal corresponding to said third count signal attaining a value indicative of the prescribed number of rows or lines per frame, said third count signal thereafter being returned to an initial value thereof.   
     
     
       4. Clock regeneration circuitry as set forth in claim 3 further comprising: a fourth counter counting occurrences of said second clock signal for generating a fourth count signal and a fifth clock signal, each occurrence of said fifth clock signal corresponding to said fourth count signal attaining a value indicative of a prescribed number of symbols per column, said fourth count signal thereafter being returned to an initial value thereof; and,   a fifth counter counting occurrences of said fifth clock signal in each line period for generating a fifth count signal.   
     
     
       5. Clock regeneration circuitry as set forth in claim 4 included in said digital signal receiver in combination with: means responding to each sample from said analog-to-digital converter for deciding a symbol value described by that sample, thereby to regenerate a respective symbol indication; and   a deinterleaver for said symbol indications including random-access memory receiving said second count signal and said third count signal as write address signals and receiving said fourth count signal and said fifth count signal as read address signals.   
     
     
       6. Clock regeneration circuitry as set forth in claim 4 included in said digital signal receiver in combination with: a ghost suppression filter receptive of samples from said analog-to-digital converter for supplying de-ghosted samples;   means responding to each de-ghosted sample for deciding a symbol value described by that sample, thereby to regenerate a respective symbol indication; and   a deinterleaver for said symbol indications including random-access memory receiving said second count signal and said third count signal as write address signals and receiving said fourth count signal and said fifth count signal as read address signals.   
     
     
       7. Clock regeneration circuitry as set forth in claim 1, wherein said frequency divider includes: a first counter counting occurrences of the oscillations of said controlled oscillator for generating a first count signal;   means detecting each time said first count signal reaches a value indicative of the prescribed number of the oscillations of said controlled oscillator per line for generating a first clock signal applied to said automatic-frequency-and-phase-control detector as said automatic-frequency-and-phase-control feedback signal; and   means applying said first clock signal to said first counter for resetting said first count signal to an initial value thereof.   
     
     
       8. Clock regeneration circuitry as set forth in claim 7 further comprising: a second counter counting occurrences of said first clock signal for generating a second count signal and a second clock signal, respective occurrences of said second clock signal corresponding to said second count signal attaining a value indicative of the prescribed number of rows or lines per frame, said second count signal thereafter being returned to an initial value thereof.   
     
     
       9. Clock regeneration circuitry as set forth in claim 8 further comprising: a third counter counting occurrences of the oscillations of said controlled oscillator for generating a third count signal and a third clock signal, respective occurrences of said third clock signal corresponding to said third count signal attaining a value indicative of the prescribed number of symbols per column, said third count signal thereafter being returned to an initial value thereof; and   a fourth counter counting occurrences of said third clock signal in each line period for generating a fourth count signal indicative of a data column within a data frame.   
     
     
       10. Clock regeneration circuitry as set forth in claim 9 included in said digital signal receiver in combination with: means responding to each sample from said analog-to-digital converter for deciding a symbol value described by that sample, thereby to regenerate a respective symbol indication; and   a deinterleaver for said symbol indications including random-access memory receiving said first count signal and said second count signal as write address signals and receiving said third count signal and said fourth count signal as read address signals.   
     
     
       11. Clock regeneration circuitry as set forth in claim 9 included in said digital signal receiver in combination with: a ghost suppression filter receptive of samples from said analog-to-digital converter for supplying de-ghosted samples;   means responding to each de-ghosted sample for deciding a symbol value described by that sample, thereby to regenerate a respective symbol indication; and   a deinterleaver for said symbol indications including random-access memory receiving said first count signal and said second count signal as write address signals and receiving said third count signal and said fourth count signal as read address signals.   
     
     
       12. Clock regeneration circuitry as set forth in claim 1 wherein said row synchronization signals consist of line synchronizing pulses included together with said analog signal representative of digital data in said received signal. 
     
     
       13. In a digital signal receiver receptive of a received signal including line synchronization pulses occurring at a line rate and including analog signal representative of digital data having a symbol rate that is a multiple of line rate, clock regeneration circuitry comprising: a controlled oscillator for generating oscillations at a frequency that is controlled in response to an automatic-frequency-and-phase-control signal and that can be controlled to be a multiple of said symbol rate;   a frequency divider for dividing the frequency of the oscillations of said controlled oscillator by a factor equal to the number of said oscillations that are supposed to occur between corresponding points in consecutive line synchronization pulses, to generate an automatic-frequency-and-phase-control feedback signal;   means for separating said line synchronization pulses from said received signal to provide separated line synchronization pulses;   a controlled delay line for delaying said separated line synchronization pulses in amount controlled by a delay control signal, thereby to provide delayed line synchronization pulses;   an automatic-frequency-and-phase-control detector for generating said automatic-frequency-and-phase-control signal responsive to differences in the respective frequencies and respective phases of said automatic-frequency-and-phase-control feedback signal and of said delayed line synchronization pulses, thereby completing a first feedback loop for applying automatic-frequency-and-phase-control signal to said controlled oscillator;   a first analog-to-digital converter responsive to the oscillations of said controlled oscillator for sampling and digitizing said analog signal representative of digital data, thereby to generate at said symbol rate digitized signal samples representative of said digital data; and   means for determining sampling phase error in said digitized signal samples generated at said symbol rate, thereby to generate said delay control signal applied to said controlled delay line for completing a supplementary feedback loop for adjusting the sampling phase in said digitized signal samples to minimize inter-symbol interference.   
     
     
       14. Clock regeneration circuitry as set forth in claim 13; wherein said first analog-to-digital converter is of an oversampling type, sampling said analog signal representative of digital data in accordance with a first clock signal supplied at an oversampling rate that is at least a two times multiple of said symbol rate, and supplying said digitized signal samples at said symbol rate in accordance with a second clock signal; and wherein said frequency divider includes: a zero-crossing detector for generating said first clock signal responsive to the oscillations of said controlled oscillator,   a first counter counting occurrences of said first clock signal for generating a first count signal and said second clock signal, each occurrence of said second clock signal corresponding to said first count signal attaining a value indicative of the prescribed number of samples per symbol period, said first count signal thereafter being returned to an initial value thereof;   a second counter counting occurrences of said second clock signal in each line period for generating a second count signal,   means detecting each time said second count signal reaches a value indicative of the prescribed number of symbols per line for generating a third clock signal applied to said automatic-frequency-and-phase-control detector as said automatic-frequency-and-phase-control feedback signal, and   means applying said third clock signal to said second counter for resetting said second count signal to an initial value thereof.   
     
     
       15. Clock regeneration circuitry as set forth in claim 13 included in said digital signal receiver together with: a line-comb filter responsive to said digitized signal samples representative of said digital data, as generated at said symbol rate by said first analog-to-digital converter, said line-comb filter including at least one line-store memory addressed by said second count signal.   
     
     
       16. Clock regeneration circuitry as set forth in claim 13 included in said digital signal receiver together with: a ghost suppression filter responsive to said digitized signal samples representative of said digital data, as generated at said symbol rate by said first analog-to-digital converter, for supplying respective de-ghosted samples;   a line-comb filter responsive to said de-ghosted samples, said line-comb filter including at least one line-store memory addressed by said second count signal.   
     
     
       17. Clock regeneration circuitry as set forth in claim 14 included in said digital signal receiver together with: a third counter counting occurrences of said third clock signal in each line period for generating a third count signal, and a fourth clock signal, respective occurrences of said fourth clock signal corresponding to said third count signal attaining a value indicative of the prescribed number of rows or lines per frame, said third count signal thereafter being returned to an initial value thereof.   
     
     
       18. Clock regeneration circuitry as set forth in claim 14 included in said digital signal receiver together with: a third counter counting occurrences of said third clock signal in each line period for generating a third count signal and a fourth clock signal, respective occurrences of said fourth clock signal corresponding to said third count signal attaining a value indicative of the prescribed number of rows or lines per frame, said third count signal thereafter being returned to an initial value thereof; and   a frame-comb filter responsive to said digitized signal samples representative of said digital data, as generated at said symbol rate by said first analog-to-digital converter, said frame-comb filter including at least one frame-store memory addressed by said second and third count signals.   
     
     
       19. Clock regeneration circuitry as set forth in claim 14 included in said digital signal receiver together with: a ghost suppression filter responsive to said digitized signal samples representative of said digital data, as generated at said symbol rate by said first analog-to-digital converter, for supplying respective de-ghosted samples;   a third counter counting occurrences of said third clock signal in each line period for generating a third count signal and a fourth clock signal, respective occurrences of said fourth clock signal corresponding to said third count signal attaining a value indicative of the prescribed number of rows or lines per frame, said third count signal thereafter being returned to an initial value thereof; and   a frame-comb filter responsive to said de-ghosted samples, said frame-comb filter including at least one frame-store memory addressed by said second and third count signals.   
     
     
       20. Clock regeneration circuitry as set forth in claim 13, wherein said frequency divider includes: a first counter counting occurrences of the oscillations of said controlled oscillator for generating a first count signal;   means detecting each time said first count signal reaches a value indicative of the prescribed number of the oscillations of said controlled oscillator per line for generating a first clock signal applied to said automatic-frequency-and-phase-control detector as said automatic-frequency-and-phase-control feedback signal; and   means applying said first clock signal to said first counter for resetting said first count signal to an initial value thereof.   
     
     
       21. Clock regeneration circuitry as set forth in claim 20 included in said digital signal receiver together with: a line-comb filter responsive to said digitized signal samples representative of said digital data, as generated at said symbol rate by said first analog-to-digital converter, said line-comb filter including at least one line-store memory addressed by said first count signal.   
     
     
       22. Clock regeneration circuitry as set forth in claim 21 included in said digital signal receiver together with: a ghost suppression filter responsive to said digitized signal samples representative of said digital data, as generated at said symbol rate by said first analog-to-digital converter, for supplying respective de-ghosted samples;   a line-comb filter responsive to said de-ghosted samples, said line-comb filter including at least one line-store memory addressed by said first count signal.   
     
     
       23. Clock regeneration circuitry as set forth in claim 20 further comprising: a second counter counting occurrences of said first clock signal for generating a second count signal and a second clock signal, respective occurrences of said second clock signal corresponding to said second count signal attaining a value indicative of the prescribed number of rows or lines per frame, said second count signal thereafter being returned to an initial value thereof.   
     
     
       24. Clock regeneration circuitry as set forth in claim 23 included in said digital signal receiver together with: a frame-comb filter responsive to said digitized signal samples representative of said digital data, as generated at said symbol rate by said first analog-to-digital converter, said frame-comb filter including at least one frame-store memory addressed by said first and second count signals.   
     
     
       25. Clock regeneration circuitry as set forth in claim 23 included in said digital signal receiver together with: a ghost suppression filter responsive to said digitized signal samples representative of said digital data, as generated at said symbol rate by said first analog-to-digital converter, for supplying respective de-ghosted samples; and   a frame-comb filter responsive to said de-ghosted samples, said frame-comb filter including at least one frame-store memory addressed by said first and second count signals.