Video signal noise suppression circuit

Abstract

Imaging apparatus includes a solid state sensor and a noise suppression circuit for suppressing noise in a video output signal generated by the image sensor.

What is claimed is: 
     
       1. A noise suppression apparatus comprising: a video signal input terminal for receiving a video signal including noise components having a reset level signal and an information level signal;   a first sample and hold circuit having an input terminal connected to said video signal input; an output terminal and a control terminal;   a subtraction circuit having a first input terminal connected to said output terminal of said first sample and hold circuit, a second input terminal, connected to said video signal input terminal, and an output terminal;   a second sample and hold circuit having an input terminal connected to said output terminal of said subtraction circuit, a control terminal, and an output terminal; and   a control circuit (a) for producing a first control signal which is applied to said control terminal of said first sample and hold circuit to control said first sample and hold circuit to sample said reset level signal of said video signal and to hold a signal value representative thereof; and (b) for producing a second control signal which is applied to said control terminal of said second sample and hold circuit to sample said sample and hold circuit to sample said information level signal of said video signal and to hold a signal value representative thereof; whereby to produce at said output terminal of said second sample and hold circuit a video signal having said noise component suppressed.   
     
     
       2. The apparatus of claim 1 wherein said subtraction circuit is a differential amplifier. 
     
     
       3. The apparatus of claim 1 wherein said first sample and hold circuit includes an input buffer amplifier, a solid state switch, a capacitor and an output buffer amplifier. 
     
     
       4. The apparatus of claim 1 wherein said second sample and hold circuit includes an input buffer amplifier, a solid state switch, a capacitor, and an output buffer amplifier.