Arrangement for generating pulse code modulation values

Abstract

Arrangement for generating pulse code modulation values in a telephone set, comprising a microprocessor which includes a working store, in which the microprocessor and the working store are connected by a data bus and an address bus, further including an output circuit for outputting the pulse code modulation values, an output memory connected thereto for storing the pulse code modulation values to be output, the working store and the output memory being incorporated in a single memory circuit. The arrangement is preferably structured in such a way that it comprises an addressing device for generating, in response to the microprocessor's addressing of a random location of the output memory, an address of an output memory location to be read out.

We claim: 
     
       1. An arrangement for generating pulse code modulation values in a telephone set, comprising: a microprocessor;   a working store for use by the microprocessor;   data bus means for coupling said microprocessor to said working store and for transmitting data from the microprocessor to the working store;   an output circuit, coupled to the microprocessor via the data bus means, for outputting the pulse code modulation values;   output memory means, coupled to the output circuit and the microprocessor via the data bus means, for storing the pulse code modulation values, said output memory means including addressable memory locations, said output circuit for reading the pulse code modulation values from the output memory means via the data bus and not from the microprocessor, the output memory means and the working store being comprised in a single memory circuit; and   address bus means for coupling the microprocessor to the working store and the output memory means and for transmitting addresses for addressing the working store and the output memory means.   
     
     
       2. The arrangement as claimed in claim 1, characterized in that the output circuit comprises a FIFO register for temporary storage of the pulse code modulation values to be output. 
     
     
       3. The arrangement as claimed in claim 1, characterized in that the output circuit comprises a parallel-to-serial converter. 
     
     
       4. The arrangement as claimed in claim 1, characterized in that the microprocessor comprises at least several combined address and data outputs. 
     
     
       5. The arrangement according to claim 1, further including addressing means, coupled to the microprocessor the working store and the output memory means, for generating and selecting an output memory location address in response to the microprocessor requesting an output memory location. 
     
     
       6. The arrangement as claimed in claim 5, characterized in that the addressing means comprises an address latch for temporary storage of a portion of the address to be read out, and wherein the data bus means carries the portion of the address to be read out instead of the address bus means carrying the portion of the address to be read out, the address latch being coupled to the data bus means. 
     
     
       7. The arrangement as claimed in claim 5, characterized in that the addressing means and the output circuit are incorporated in an application-specific integrated circuit. 
     
     
       8. The arrangement as claimed in claim 5, wherein the addressing means comprises: a) an address register for generating addresses of the output memory locations;   b) multiplexing means coupled to the address bus means for connecting the address bus to the working store and for connecting the address register to the output memory means;   c) address decoding means for decoding addresses generated by the microprocessor into addresses for addressing the working store and addresses for addressing the output memory means and for causing the multiplexing means to connect the address bus to the working store, and the address register to the output memory means.   
     
     
       9. The arrangement as claimed in claim 8, wherein said address register serially increments the output memory location address. 
     
     
       10. The arrangement as claimed in claim 9, wherein the addressing means further comprises: a final value register containing a predetermined number; and   a comparator for comparing the predetermined number with the address contained in the address register and for resetting the address register if the address contained in the address register equals the predetermined number.   
     
     
       11. The arrangement as claimed in claim 10, wherein the addressing means further comprises an address latch for temporary storage of a portion of an address to be read out, and wherein the data bus means carries the portion of the address to be read out instead of the address bus means carrying the portion of the address to be read out, the address latch being coupled to the data bus means. 
     
     
       12. The arrangement as claimed in claim 11, characterized in that the output circuit comprises a FIFO register for temporary storage of the pulse code modulation values to be output. 
     
     
       13. The arrangement as claimed in claim 12, characterized in that the output circuit comprises a parallel-to-serial converter. 
     
     
       14. The arrangement as claimed in claim 13, characterized in that the microprocessor comprises at least several combined address and data outputs. 
     
     
       15. The arrangement as claimed in claim 14, characterized in that the addressing means and the output circuit are incorporated in an application-specific integrated circuit. 
     
     
       16. An arrangement for generating pulse code modulation values in a telephone set, comprising: a microprocessor;   a working store for use by the microprocessor;   data bus means for coupling the microprocessor to the working store and for transmitting data from the microprocessor to the working store;   an output circuit, coupled to the microprocessor via the data bus means, for outputting the pulse code modulation values;   output memory means, coupled to the output circuit and the microprocessor via the data bus means, for storing the pulse code modulation values, the output memory means including addressable memory locations, the working store and the output memory means being comprised in a single memory circuit;   address bus means for coupling the microprocessor to the working store and the output memory means and for transmitting addresses for addressing the working store and the output memory means; and   addressing means, coupled to the microprocessor, the address bus means, the working store and the output memory means, for generating and selecting an output memory location address in response to the microprocessor requesting an output memory location.