Vertical synchronous signal separation apparatus

Abstract

A vertical synchronous signal separation circuit is disclosed wherein the circuit includes a vertical synchronous pulse removal circuit for delaying original horizontal and vertical synchronous signals separated from a composite video signal by a predetermined time period in response to a reference clock signal and logically combining the original horizontal and vertical synchronous signals with the delayed horizontal and vertical synchronous signals to remove vertical synchronous pulses therefrom, a clock generator for logically combining an output signal from the vertical synchronous pulse removal circuit with the reference clock signal to generate a clock signal, an edge detector for detecting edges of the output signal from the vertical synchronous pulse removal circuit and outputting the detected edges as a reset signal, and a vertical synchronous signal extractor for extracting a stable vertical synchronous signal from the original horizontal and vertical synchronous signals in response to the clock signal from the clock generator and the reset signal from the edge detector.

What is claimed is: 
     
       1. A vertical synchronous signal separation apparatus comprising: vertical synchronous pulse removal means for delaying original horizontal and vertical synchronous signals separated from a composite video signal by a predetermined time period in response to a reference clock signal and logically combining the original horizontal and vertical synchronous signals with the delayed horizontal and vertical synchronous signals to remove vertical synchronous pulses therefrom;   clock generation means for logically combining an output signal from said vertical synchronous pulse removal means with the reference clock signal to generate a clock signal;   edge detection means for detecting edges of the output signal from said vertical synchronous pulse removal means and outputting the detected edges as a reset signal; and   vertical synchronous signal extraction means for extracting a stable vertical synchronous signal from the original horizontal and vertical synchronous signals in response to the clock signal from said clock generation means and the reset signal from said edge detection means.   
     
     
       2. A vertical synchronous signal separation apparatus as set forth in claim 1, wherein said vertical synchronous pulse removal means includes: delay means for delaying the original horizontal and vertical synchronous signals by the predetermined time period in response to the reference clock signal; and   an AND gate for ANDing the original horizontal and vertical synchronous signals with the delayed horizontal and vertical synchronous signals from said delay means to remove the vertical synchronous pulses therefrom.   
     
     
       3. A vertical synchronous signal separation apparatus as set forth in claim 2, wherein said delay means includes: a plurality of D flip-flops for delaying the original horizontal and vertical synchronous signals by the predetermined time period in response to the reference dock signal.   
     
     
       4. A vertical synchronous signal separation apparatus as set forth in claim 1, wherein said vertical synchronous signal extraction means includes: counting means for counting the clock signal from said clock generation means in response to the reset signal from said edge detection means; and   latch means for latching an output signal from said counting means in response to the reset signal from said edge detection means to output the stable vertical synchronous signal.   
     
     
       5. A vertical synchronous signal separation apparatus as set forth in claim 4, wherein said counting means includes: an octal counter having a plurality of T flip-flops for counting the clock signal from said clock generation means in response to the reset signal from said edge detection means.   
     
     
       6. A vertical synchronous signal separation apparatus as set forth in claim 5, wherein said latch means includes: a first NOR gate having one input terminal for inputting the reset signal from said edge detection means;   a second NOR gate having one input terminal for inputting an output signal from said first NOR gate, the other input terminal for inputting an output signal from said octal counter and an output terminal connected to the other input terminal of said first NOR gate; and   an inverter for inverting an output signal from said second NOR gate to output the stable vertical synchronous signal.