Processor having different operand source information temporarily stored in plural holding registers to avoid using microprogram ROM capacity for such information

Abstract

An information processing apparatus executes a machine language instruction according to a microprogram controlling method. The apparatus comprises an instruction decoder for decoding the machine language instruction; an operand controller for receiving from the instruction decoder, information about operands that are necessary in executing the machine language instruction, and fetching and holding the operands according to the information; and an instruction executing device generating operand requests to the operand controller, obtaining the operands, and executing the machine language instruction under the control of a microprogram. Thus, the apparatus can execute a plurality of machine language instructions that respectively prescribe the same operation to be carried out on the different kinds of operands, under the control of a single microprogram irrespective of the differences of the kinds of the operands.

What is claimed is: 
     
       1. A microprogram controlling method for executing machine language instructions by using microprograms, said method comprising the steps of: decoding a machine language instruction in a decoding means, and obtaining information specifying a microprogram to be used for executing said machine language instruction, information about operands to be used for execution of said machine language instruction and information including an operational code which is common to machine language instructions differing only in an operand source;   sending said information about said operands to operand controlling means and storing said information about said operands in said operand controlling means, said operand controlling means storing at least an immediate operand and an address of a memory as information about operands of a single machine language instruction at the same time;   checking by said operand controlling means to see whether or not information about memory operands exists among said information about said operands stored in said operand controlling means;   if it is judged by said checking step that information about a memory operand is held in said operand controlling means, carrying out a plurality of operand fetch operations for one microinstruction by accessing an external memory according to said information about said memory operands and fetching said memory operands for said operand controlling means;   sending said information specifying said microprogram to microprogram storing means;   reading a microinstruction constituting said microprogram from said microprogram storing means according to said information specifying said microprogram;   sending an operand request signal which does not depend on the kind of operand from said microinstruction to said operand controlling means; and   outputting a requested operand to a local bus from said operand controlling means according to said operand request signal.   
     
     
       2. A microprogram controlling method for executing machine language instructions by using microprograms, said method comprising the steps of: decoding a machine language instruction by a decoding means, and obtaining first information specifying a microprogram to be used for executing said machine language instruction and second information about operands to be used in execution of said machine language instruction, said second information including information concerning whether each operand is a memory operand, a register operand or an immediate operand, an address in a memory if said operand is a memory operand and an identification number in a register set if said operand is a register operand;   storing said second information about said operands in selected ones of operand information holding means, in such a way that a value of an immediate operand, if any, is stored in a first predetermined section of one of said operand information holding means selected for holding said information about said immediate operand, and wherein said immediate operand is stored in a second predetermined section in one of said operand information holding means at the same time an address of a memory is stored in a predetermined section in another of said operand information holding means;   checking by memory access controlling means to see whether or not said information stored in any of said selected ones of said operand information holding means relates to memory operands;   if an operand information holding means is judged by said checking step to be holding information which relates to said memory operands, controlling memory access by said memory access controlling means by carrying out a plurality of operand fetch operations for one microinstruction by accessing said memory according to a memory address of said memory operands stored in said operand information holding means, and fetching said memory operands for said operand information holding means;   sending said first information specifying said microprogram to a microprogram storing means;   reading a microinstruction constituting said microprogram from said microprogram storing means according to said first information;   sending an operand request signal which does not depend on the kind of operand, from said microinstruction to selecting means which stores information about a selection carried out in selecting several ones out of a predetermined number of said operand information holding means to store information about said operands;   selecting by said selecting means, an operand information holding means which holds information about an operand specified by said operand request signal; and   if a selected operand information holding means is holding information about a memory operand or an immediate operand, outputting said value of said operand stored in said first predetermined section of said selected operand information holding means to a local bus, and, if said selected operand information holding means is holding information about a register operand, sending an identification number of a register stored in a second predetermined section of said selected operand information holding means to a register set, selecting said register from said register set according to said identification number, and outputting the contents of said register to said local bus, thereby obtaining said operand requested by said microinstruction on said local bus.   
     
     
       3. A processor for microprograms comprising: an instruction decoder for decoding a machine language instruction and outputting a decoded machine language instruction including an operational code which is common to machine instructions differing only in an operand source and outputting a starting address of a microinstruction corresponding to said operational code;   a memory for storing said microprograms and for outputting a series of microinstructions in response to said starting address of said microinstruction corresponding to said operational code of said decoded machine language instruction outputted from said instruction decoder;   a micro-decoder for decoding microinstructions of said series of micro instructions outputted from said memory and outputting control signals;   operand information holding means for receiving information from said instruction decoder and for holding said information about a plurality of operands of said decoded machine language instruction outputted from said instruction decoder indicative of addresses of said operands and indicative of operand sources from which said operands should be fetched, said operand information holding means holding at least an immediate operand and an address of a memory of the machine language instruction at the same time; and   controlling means for selectively carrying out a plurality of operand fetch operations from general registers and/or from an external memory for one microinstruction in accordance with said information about said operands transferred from said holding means upon receipt of said control signals outputted from said micro-decoder.   
     
     
       4. The processor as claimed in claim 3, wherein there are a predetermined number of said operand information holding means for holding said information about said operands. 
     
     
       5. The processor as claimed in claim 4, wherein said controlling means comprises selecting means for storing information concerning which of said operands is to be used in executing said machine language instruction which is stored in said operand information holding means, for receiving an operand selecting signal from said micro-decoder, and selecting one of said operand information holding means which holds information about an operand specified by said operand selecting signal according to said information concerning which of said operands is to be used in executing said machine language instruction which is stored in said operand information holding means. 
     
     
       6. The processor of claim 3, wherein said operand information holding means comprises a plurality of registers, each register of said registers containing information about one operand. 
     
     
       7. The processor of claim 6, wherein each register of said registers of said operand information holding means holds bits indicative of operand data, bits indicative of an address of an operand, a bit indicative of whether or not a required operand exists in one of said general registers and a bit indicative of whether or not access to said external memory is required. 
     
     
       8. A processor for microprograms comprising: an instruction decoder for decoding a machine instruction and outputting a decoded machine instruction including an operational code which is common to machine instructions differing only in an operand source;   a memory for storing said microprograms and outputting a series of microinstructions in response to a starting address of a microinstruction corresponding to said operational code of said decoded machine instruction outputted from said instruction decoder;   a micro-decoder for decoding a microinstruction outputted from said memory and outputting a control signal;   a predetermined number of operand information holding means for receiving from said instruction decoder and respectively holding information about operands of said decoded machine instruction outputted from said instruction decoder indicative of addresses of said operands and indicative of an operand source from which said operands should be fetched, said operand information holding means storing an immediate operand and an address of a memory of the machine instruction at the same time, wherein each of said operand information holding means includes a first information holding section for holding information concerning whether or not memory access is needed concerning an operand held in a respective operand information holding means,   a second information holding section for holding information concerning whether said memory access needed is a reading access or a writing access,   a third information holding section for holding information concerning a memory address, which is used in said memory access, of an operand held in a respective operand information holding means if said operand held in said respective operand information holding means is a memory operand and for holding information about a register number if said operand held in said respective operand information holding means is a register operand,   a fourth information holding section for holding information about validity of a value of an operand held in said operand information holding means,   a fifth information holding section for holding information concerning whether said information held in said third information holding section is valid or invalid, and   a sixth information holding section for holding information concerning whether said information held in said third information holding section concerns said memory address or said register number; and     controlling means for alternatively carrying out an operand fetch operation from general registers or an external memory in accordance with said information about one of said operands transferred from said operand information holding means upon receipt of said control signal outputted from said micro-decoder.   
     
     
       9. The processor as claimed in claim 8, wherein said controlling means comprises: memory access controlling means for   receiving information held in said first and second information holding sections of each of said operand information holding means,   reading said memory according to information held in said third information holding section of said operand information holding means if there is a memory reading request in a respective operand information holding means, and   setting a result of reading said memory in said fourth information holding section of said operand information holding means.   
     
     
       10. An apparatus for executing instructions comprising: an instruction decoder for decoding a machine language instruction in sequence to generate a first decoded signal including information about a plurality of operands and a second decoded signal indicative of a microprogram executable using said plurality of operands, wherein said plurality of operands is obtained in accordance with said information, and wherein said information for each of said plurality of operands including at least one of an immediate operand, an operand address or a register number;   storing means, connected to said instruction decoder, for receiving and storing said information about said plurality of operands from said instruction decoder, said storing means being capable of storing said information for each of said plurality of operands of the machine instruction including an immediate operand and an address of a memory at the same time;   a microprogram storing block connected to said instruction decoder for storing microprograms and outputting microinstructions in sequence in accordance with said second decoded signal;   a microinstruction register connected to said microprogram storing block for holding microinstructions;   a micro-decoder connected to said microinstruction register for decoding a microinstruction in sequence and generating a plurality of control signals for executing said microprograms;   a selector connected to said storing means and said micro-decoder for receiving a control signal from said micro-decoder and controlling said storing means to selectively output to said controller said information about said plurality of operands for executing said microinstructions decoded by said micro-decoder;   a controller connected to said storing means for providing operands on a local bus based on said information; and   an arithmetic logic unit connected to said local bus for executing microinstructions based on said operands.   
     
     
       11. The apparatus as claimed in claim 10, wherein said means stores a first information bit of said information, indicative of whether a corresponding operand is stored in a general register. 
     
     
       12. The apparatus as claimed in claim 10, wherein said means stores second information bits of said information, indicative of whether the items of said information contains a valid operand. 
     
     
       13. The apparatus as claimed in claim 10, wherein said means stores third information bits of said information, indicative of whether the items of said information contain a valid address of a corresponding operand. 
     
     
       14. The apparatus as claimed in claim 10, wherein said means stores a fourth information bit of said information, indicative of whether a corresponding operand is stored in an external memory.