Semiconductor integrated delay circuit

Abstract

A semiconductor integrated circuit having a plurality of power source voltages in one chip and which comprises delaying means which accurately implements a predetermined delay time into a signal. An inverter circuit block receives at its input part an output from a NAND gate. An output from the inverter circuit block is coupled to a node of a phase comparing part through a switch. The output from the inverter circuit block is also coupled through another switch to an input part of another inverter circuit block whose output is coupled to the node of the phase comparing part through still another switch. A control signal is set at a L level if the phase comparing part is to operate at a first power source voltage and set at a H level if the phase comparing part is to operate at a second power source voltage which is larger than the first power source voltage.

We claim: 
     
       1. A semiconductor integrated circuit to which a plurality of voltage levels of power source voltage are applied, comprising: ground level voltage providing means for providing a ground level, said ground level being a fixed voltage;   a plurality of signal delaying means operably connected to said power source voltage for delaying a signal received therein by a predetermined time and outputting a delayed signal, said signal delaying means comprising a plurality of series-connected inverters, said plurality of series-connected inverters each defining a H level by said power source voltage and a L level by said ground level; and   controllable delaying path synthesizing means operably connected to said plurality of signal delaying means for selectively combining input and output parts of at least one of said plurality of signal delaying means in accordance with a control signal responsive to a corresponding voltage level of said plurality of voltage levels of said power source voltage to thereby synthesize a delaying path through which a signal is always delayed by a fixed predetermined time.   
     
     
       2. The semiconductor integrated circuit of claim 1, wherein said controllable delaying path synthesizing means includes: a plurality of switching means each interposed between input parts and output parts of a respective one of said plurality of signal delaying means; and   delaying path combining means which receives said power source voltage, turns on and off said plurality of switching means in accordance with the voltage level of said power source voltage, and which combines input parts and output parts of one or more of said plurality of signal delaying means through said switching means which are in their On-state, whereby a delaying path is created which always delays a signal by a fixed predetermined time.   
     
     
       3. A semiconductor integrated circuit, comprising: power source voltage providing means for providing a power source voltage of a first voltage level or alternately a power source voltage of a second voltage level which is higher than said first voltage level;   ground level voltage providing means for providing a ground level, said ground level being a fixed voltage;   first delaying means having an input part and an output part, said first delaying means comprising a plurality of series-connected inverters, each of which defining a H level by said power source voltage and a L level by said ground level, said first delaying means delaying a signal received at the input part thereof by a first delay time in response to said power source voltage of said first voltage level and outputting a delayed signal from the output part thereof, while delaying a signal received at the input part thereof by a second delay time in response to said power source voltage of said second voltage level and outputting a delayed signal from the output part thereof;   second delaying means having an input part and an output part, said second delaying means comprising a plurality of series-connected inverters each of which defining a H level by said power source voltage and a L level by said ground level, said second delaying means delaying a signal received at the input part thereof by a third delay time in response to said power source voltage of said second voltage level and thereafter outputting a delayed signal from the output part thereof, said third delay time being a difference between said first delay time and said second delay time which is shorter than said first delay time; and   delaying path determining means for determining said first delaying means as a signal delaying path when said power source voltage has said first voltage level and for combining said output part of said first delaying means and said input part of said second delaying means and determining a combining path of said first and said second delaying means as said signal delaying path when said power source voltage has said second voltage level to provide a fixed predetermined signal delay time.   
     
     
       4. A semiconductor integrated circuit to which a power source voltage of either a first voltage level or a second voltage level which is higher than said first voltage level is applied, comprising: a delayed signal output part, a conductive path from said delayed signal output part to a signal input part being a signal delaying path;   first switching means, an input part of said first switching means being connected to an output part of a first delaying means, an output part of said first switching means being connected to said delayed signal output part;   second switching means, an input part of said second switching means being connected to said output part of said first delaying means, an output part of said second switching means being connected to an input of a second delaying means;   third switching means, an input part of said third switching means being connected to an output part of said second delaying means, an output part of said third switching means being connected to said delayed signal output part; and   switching control means for turning on said first switching means and turning off said second and said third switching means in response to said power source voltage of said first voltage level and for turning off said first switching means and turning on said second and said third switching means in response to said power source voltage of said second voltage level.   
     
     
       5. The semiconductor integrated circuit of claim 4, wherein said first to said third switching means each have a signal control part and turn on and off respectively in response to a first logical level and a second logical level received at its signal control part, and wherein said switching control means is:   responsive to said power source voltage of said first voltage level to give a control signal of said first logical level to said signal control part of said first switching means and to give a control signal of said second logical level to said signal control parts of said second and said third switching means; and   responsive to said power source voltage of said second voltage level to give a control signal of said second logical level to said signal control part of said first switching means and to give a control signal of said first logical level to said signal control parts of said second and said third switching means.   
     
     
       6. The semiconductor integrated circuit of claim 5, further comprising: phase comparison means for receiving a first input signal and a second input signal and outputting a pulse signal, which has a pulse width corresponding to a phase difference between the first input signal and the second input signal, as either a first output signal or a second output signal, said phase comparison means outputting an inner signal to a signal input part of said signal delaying path, and inputting a delay signal outputted from a signal output part of said signal delaying path as an inner signal.   
     
     
       7. The semiconductor integrated circuit of claim 6, wherein said phase comparison means generates a pulse signal which has a pulse width which corresponds to a phase difference between said first input signal and said second input signal and outputs said pulse signal as said first output signal therefrom if said first input signal leads said second input signal and outputs said pulse signal as said second output signal therefrom if said second input signal leads said first input signal. 
     
     
       8. The semiconductor integrated circuit of claim 7, wherein if said first input signal leads said second input signal, said phase comparison means generates a pulse signal which has a pulse width which is equal to a sum of a phase lead and a first delay time and outputs the pulse signal as said first output signal therefrom, concurrently with which said phase comparison means generates a pulse signal which has a pulse width which is equal to said first delay time and outputs the pulse signal as said second output signal therefrom, and wherein if said second input signal leads said first input signal, said phase comparison means generates a pulse signal which has a pulse width which is equal to a sum of a phase lead and said first delay time and outputs the pulse signal as said second output signal therefrom, concurrently with which said phase comparison means generates a pulse signal which has a pulse width which is equal to said first delay time and outputs the pulse signal as said first output signal therefrom. 
     
     
       9. A semiconductor integrated circuit, comprising: fixed voltage providing means for providing a fixed voltage of a predetermined voltage level which is independent from the influence of a variation in the power source voltage;   ground level voltage providing means for providing a ground level voltage; and   signal delaying means for delaying a signal received therein by a fixed predetermined time and outputting a delayed signal, said signal delaying means comprising a plurality of series-connected inverters, said plurality of series-connected inverters each defining a H level by said fixed voltage and a L level by said ground level voltage.   
     
     
       10. The semiconductor integrated circuit of claim 9, wherein said fixed voltage providing means comprises a constant voltage circuit which receives a power source voltage and said ground level voltage and which outputs a fixed voltage of a predetermined voltage level.