US5436943AExpiredUtility

Digital audio signal processing circuit

Assignee: US ARMYPriority: Jun 12, 1992Filed: Jun 12, 1992Granted: Jul 25, 1995
Est. expiryJun 12, 2012(expired)· nominal 20-yr term from priority
Inventors:Gary S. Borgen
G11B 20/22G11B 20/10527
33
PatentIndex Score
2
Cited by
3
References
6
Claims

Abstract

A digital audio signal processing circuit for eliminating the amplitude and phase components of logic induced modulation from a left right clock signal, a bit clock signal and digital data bits generated by a digital signal processor within a compact disk player. The digital audio signal processing circuit includes a trio of optical couplers for removing the amplitude component of logic induced modulation from the left right clock signal, the bit clock signal and the digital data bits; a clock circuit for generating a system clock signal and a trio of D Flip-Flops for removing the phase component of logic induced modulation from the left right clock signal, the bit clock signal and the digital data bits and a digital to analog converter for separating the data bits into left channel data bits and right channel data bits and for converting the left channel data bits into a first analog signal and the right channel data bits into a second analog signal for use by speakers or the like to provide stereo sound. An isolated power supply provides both analog and digital voltages to the electronic elements of digital audio signal processing circuit.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A digital audio signal processing circuit for eliminating jitter from a left right clock signal, a bit clock signal and digital data words generated by a digital signal processor, said digital signal processor having a clock input and a muting output, said digital audio processing circuit comprising: a first inverter having an input adapted to receive said left right clock signal and an output;   a second inverter having an input adapted to receive said bit clock signal and an output;   a first optical coupler having a signal input connected to the output of said first inverter, an enable input and a signal output;   a second optical coupler having a signal input connected to the output of said second inverter, an enable input and a signal output;   a first Flip-Flop having a data input connected to the signal output of said first optical coupler, a clock input and an output;   a second Flip-Flop having a data input connected to the signal output of said second optical coupler, a clock input and an output;   a third inverter having an input connected the muting output of said digital signal processor and an output;   a first NAND gate having a first input adapted to receive said digital data words, a second input connected to the output of said third inverter and an output;   a third optical coupler having a signal input connected to the output of said first NAND gate, an enable input and a signal output;   a third Flip-Flop having a data input connected to the signal output of said third optical coupler, a clock input and an output;.   a digital to analog converter having a left right clock input connected to the output of said first Flip-Flop, a bit clock input connected to the output of said second Flip-Flop, a serial data input connected to the output of said third Flip-Flop, a reset input, a clock input, a digital power input, positive and negative analog power inputs and first and second analog signal outputs;   a clock circuit having an output connected to the clock inputs of said first, second and third Flip-Flops and the clock input of said digital to analog converter;   a power supply having a digital power output connected to the enable inputs of said first, second and third optical couplers and the digital power input of said digital to analog converter, a positive analog power output connected to the positive analog power input of said digital to analog converter and a negative analog power output connected to the negative analog power input of said digital to analog converter;   a fourth optical coupler having a signal input connected to the output of said clock circuit, an enable input and a signal output connected to the clock input of said digital signal processor; and   a fourth inverter connected between the output of said clock circuit and the signal input of said fourth optical coupler.   
     
     
       2. The digital audio signal processing circuit of claim 1 further comprising a first low pass filter connected to the first analog signal output of said digital to analog converter and a second low pass filter connected to the second analog signal output of said digital to analog converter. 
     
     
       3. The digital audio signal processing circuit of claim 1 further comprising a circuit for resetting said digital to analog converter, said circuit comprising: fifth and sixth inverters connected in series, each of said inverters having an input and an output, the output said sixth inverter being connected to the reset input of said digital to analog converter;   a series connected resistor and capacitor, said resistor being connected to the digital power output of said power supply and said capacitor being connected to ground, the input of said fifth inverter being connected between said resistor and said capacitor; and   a diode having an anode connected to the input of said fifth inverter and a cathode connected to the digital power output of said power supply.   
     
     
       4. The digital audio signal processing circuit of claim 1 wherein said power supply comprises: a power module having an input adapted to receive one hundred fifteen volts alternating current and an output connected to the enable inputs of said first, second and third optical couplers and the digital power input of said digital to analog converter;   a direct current to direct current converter having an input connected to the output of said power module, a positive voltage output and a negative voltage output;   said direct current to direct current converter operating at a frequency substantially above the audio frequency range;   a first voltage regulator having an input connected to the positive voltage output of said converter and an output connected to the positive analog power input of said digital to analog converter; and   a second voltage regulator having an input connected to the negative voltage output of said converter and an output connected to the negative analog power input of said digital to analog converter.   
     
     
       5. A digital audio signal processing circuit for eliminating jitter from a left right clock signal, a bit clock signal and digital data words provided by a digital signal processor to a digital to analog converter, said digital signal processor having a muting output and a clock input, said digital to analog converter having a left right clock input, a bit clock input, a serial data input and a clock input, said digital audio signal processing circuit comprising: a first inverter having an input adapted to receive said left right clock signal and an output;   a second inverter having an input adapted to receive said bit clock signal and an output;   a first optical coupler having a signal input connected to the output of said first inverter, and a signal output;   a second optical coupler having a signal input connected to the output of said second inverter and a signal output;   a first Flip-Flop having a data input connected to the signal output of said first optical coupler, a clock input and an output connected to the left right clock input of said digital to analog converter;   a second Flip-Flop having a data input connected to the signal output of said second optical coupler, a clock input and an output connected to the bit clock input of said digital to analog converter;   a third inverter having an input connected the muting output of said digital signal processor and an output;   a first NAND gate having a first input adapted to receive said digital data words, a second input connected to the output of said third inverter and an output;   a fourth inverter having an input connected to the output of said first NAND gate and an output   a third optical coupler having a signal input connected to the output of said fourth inverter, an enable input and a signal output;   a third Flip-Flop having a data input connected to the signal output of said third optical coupler, a clock input and an output connected to the serial data input of said digital to analog converter;   a clock circuit having an output connected to the clock inputs of said first, second and third Flip-Flops;   a fifth inverter having an input connected to the output of said clock circuit and an output; and   a fourth optical coupler having a signal input connected to the output of said fourth inverter, an enable input and a signal output connected to the clock input of said digital signal processor.   
     
     
       6. The digital audio signal processing circuit of claim 5 further comprising: a sixth inverter having an input for receiving an external clock signal and an output;   a second NAND gate having a first input connected to the output of said sixth inverter, a second input and an output connected to the clock input of said digital signal processor; and   a switch having a first input for receiving a logic one signal, a second input for receiving a logic zero signal and an output connected to the second input of said second NAND gate and the enable input of said fourth optical coupler.

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