Inverter current load detection and disable circuit

Abstract

A circuit and method for protecting a voltage inverter circuit is disclosed. The circuit comprises a first comparison circuit capable of comparing a first reference voltage to a voltage indicative of the load current of the voltage inverter. When the comparison circuit signals that the first reference voltage is greater than the load voltage, a disable circuit coupled to the first comparison circuit disables the voltage inverter. In the preferred embodiment, the inverter provides power to a cold cathode fluorescent lamp which, if damaged, can harm the inverter.

What is claimed is: 
     
       1. A circuit for protecting a voltage inverter, comprising: a circuit for sensing a load current of said voltage inverter and for providing a voltage indicative thereof:   a first comparison circuit capable of comparing a first reference voltage to said voltage indicative of said load current of said voltage inverter; and   a disable circuit capable of disabling said voltage inverter when said first comparison circuit signals that said first reference voltage is greater than said voltage indicative of said load current, said disable circuit comprising a second comparison circuit capable of comparing a second reference voltage to a third reference voltage, said second reference voltage applied to said second comparison circuit when said first comparison circuit signals that said first reference voltage is greater than said voltage indicative of said load current, said disable circuit operative in response to said second reference voltage being greater than said third reference voltage.   
     
     
       2. The circuit as recited in claim 1 wherein said first comparison circuit is an n channel FET having a source of said n channel FET coupled to said voltage indicative of said load current and a gate of said n channel FET coupled to said first reference voltage, wherein said n channel FET is turned on when said first reference voltage is greater than said voltage indicative of said load current, resulting in said voltage indicative of said load current being applied to a drain of said n channel FET. 
     
     
       3. The circuit as recited in claim 2 wherein said second comparison circuit is a comparator. 
     
     
       4. The circuit as recited in claim 1 wherein said disable circuit further comprises: a signal line, capable of providing a signal to said voltage inverter, directing said inverter to power down, said line operative in response to a resolution that said second reference voltage is greater than said third reference voltage. 
     
     
       5. The circuit as recited in claim 4 wherein said first reference voltage is equal to said third reference voltage. 
     
     
       6. The circuit as recited in claim 1 wherein said load current is applied to a cold cathode fluorescent lamp. 
     
     
       7. A circuit for protecting a voltage inverter, comprising: a circuit for sensing a load current of said voltage inverter and for providing a voltage indicative thereof;   first means for comparing a first reference voltage to said voltage indicative of said load current of said voltage inverter; and   means for disabling said voltage inverter, said disabling means operative in response to a resolution by said first comparing means that said first reference voltage is greater than said voltage indicative of said load current, said disabling means comprising: second means for comparing a second reference voltage to a third reference voltage; and   means for applying said second reference voltage to said second comparing means, said applying means operative in response to said resolution by said first comparing means that said first reference voltage is greater than said voltage indicative of said load current, wherein said disabling means is operative in response to said second reference voltage being greater than said third reference voltage.     
     
     
       8. The circuit as recited in claim 7 wherein said first comparing means is an n channel FET having a source of said n channel FET coupled to said voltage indicative of said load current and a gate of said n channel FET coupled to said first reference voltage, wherein said n channel FET is turned on when said first reference voltage is greater than said voltage indicative of said load current resulting in said voltage indicative of said load current being applied to a drain of said n channel FET. 
     
     
       9. The circuit as recited in claim 8 wherein said applying means is a p channel FET having a gate of said p channel FET coupled to said drain of said n channel FET and having a source of said p channel FET coupled to said second reference voltage, wherein said second reference voltage is applied to a drain of said p channel FET when said second reference voltage is greater than said voltage indicative of said load current applied to said gate of said p channel FET. 
     
     
       10. The circuit as recited in claim 7 wherein said load current is applied to a cold cathode fluorescent lamp. 
     
     
       11. The circuit as recited in claim 10 wherein said disabling means further comprises: means for providing a signal to said voltage inverter directing said inverter to power down, said providing means operative in response to a resolution that said second reference voltage is greater than said third reference voltage.   
     
     
       12. The circuit as recited in claim 11 wherein said first reference voltage is equal to said third reference voltage. 
     
     
       13. A method for protecting a voltage inverter, said method comprising the steps of: sensing the load current of said voltage inverter and providing a voltage indicative of the sensed load current;   comparing a reference voltage to the voltage indicative of the load current of said inverter circuit;   sending a signal when said first reference voltage is greater than the voltage indicative of said load current;   receiving said signal;   applying a second reference voltage in response to said received signal;   comparing said second reference voltage to a third reference voltage; and   sending a disabling signal to said voltage inverter when said second reference voltage is greater than said third reference voltage.   
     
     
       14. The method as recited in claim 13 wherein said disabling signal directs said voltage inverter to power down. 
     
     
       15. The method as recited in claim 13 wherein said first reference voltage is equal to said third reference voltage. 
     
     
       16. A system for providing power to a lamp, comprising: an inverter having an input coupled to a direct current bus and an output for delivering an alternating current;   means for producing a voltage, said produced voltage being a function of current passing through said inverter output;   first means for comparing said produced voltage with a first reference voltage; and   means for decoupling said inverter from said direct current bus when said reference voltage is greater than said produced voltage, wherein said decoupling means comprises: second means for comparing a second reference voltage to a third reference voltage; and   means for applying said second reference voltage to said second comparing means, said applying means operative in response to said resolution by said first comparing means that said first reference voltage is greater than said produced voltage, wherein said decoupling means is operative in response to said second reference voltage being greater than said third reference voltage.     
     
     
       17. The system as recited in claim 16 wherein said fluorescent lamp is a cold cathode fluorescent lamp. 
     
     
       18. The system as recited in claim 16 wherein said lamp is a fluorescent lamp. 
     
     
       19. The system as recited in claim 16 wherein said inverter comprises a plurality of switches which pulse width modulate direct current delivered to said inverter via said direct current bus to produce said alternating current having a substantially sinusoidal waveform. 
     
     
       20. The system as recited in claim 16 wherein said direct current bus is coupled to a direct current power supply. 
     
     
       21. The system as recited in claim 20 wherein said direct current power supply is a battery. 
     
     
       22. The system as recited in claim 16 wherein said producing means comprises means for storing a voltage produced by a transformer coupled to said inverter output. 
     
     
       23. The system as recited in claim 16 wherein said comparing means is a FET having a source coupled to said producing means and a gate coupled to said reference voltage, wherein said FET is turned on when said reference voltage is greater than said produced voltage, resulting in said produced voltage being applied to a drain of said FET.