One clock address pipelining in segmentation unit

Abstract

A microprocessor which comprises a three input adder, a two input adder, apparatus for providing the components of a virtual address to the first and second adders on a first clock period, and apparatus for providing a segment base address to the first adder on the first clock period, apparatus for determining the type of addresses generated by the adders on a second clock period and for generating an output address on the second clock period, and apparatus for determining access violations during a third clock period.

What is claimed is: 
     
       1. In a microprocessor device, a method for generating addresses for consecutive memory references comprising the steps of: a) receiving a first signal identifying a first set of address components for a first linear address and a first effective address for a first memory reference on a first clock cycle;   b) generating said first linear address and said first effective address for said first memory reference from said first set of address component on a second clock cycle;   c) receiving a second signal identifying a second set of address components for a second linear address and a second effective address for a second memory reference on said second clock cycle; and   d) generating said second linear address and said second effective address for said second memory reference from said second set of address components on a third clock cycle.   
     
     
       2. The method as recited in claim 1 is further comprised of the step of performing a validity check of said first effective address in said third clock cycle. 
     
     
       3. The method as recited in claim 1 wherein said step b) is further comprised of the steps of: a) calculating said first linear address from said first set of a address components; and   b) calculating said first effective address from a subset of said first set of address components.   
     
     
       4. A microprocessor circuit for providing both a linear address and an effective address for a memory reference during consecutive clock periods comprising: means for providing signals representing a first plurality of address components corresponding to a first memory reference to a first and second combining means during a first clock period, said first plurality of address components being selected by a first start address formation signal issued in said first clock period, and a second plurality of address components corresponding to a second memory reference to said first and second combining means during a second clock period, said second plurality of address components being selected by a second start address formation signal issued in said second clock period, said second clock period being consecutive to said first clock period;   said first combining means for combining the signals representing said first plurality of address components to provide an effective address for said first memory reference during said second clock period and for combining the signals representing said second plurality of address components to provide an effective address for said second memory reference during a third clock period consecutive to said second clock period;   means for providing signals representing a first segment base address corresponding to said first memory reference during said first clock period and a second segment base address corresponding to said second memory reference during said second clock period to said second combining means; and   said second combining means for combining the signals representing said first plurality of address components and said first segment base address to provide a linear address for said first memory reference during said second clock period and for combining the signals representing said second plurality of address components and said second segment base address to provide a linear address for said second memory reference during said third clock period.   
     
     
       5. The microprocessor circuit as claimed in claim 4 in which the first combining means comprises a two input adder. 
     
     
       6. The microprocessor circuit as claimed in claim 4 in which the second combining means comprises a three input adder. 
     
     
       7. The microprocessor circuit as claimed in claim 4 further comprising means for determining access violations for a memory reference subsequent to the generation of a corresponding effective address and a corresponding linear address. 
     
     
       8. The microprocessor circuit as claimed in claim 4 in which the means for providing signals representing said first and said second plurality of address components comprises first and second multiplexors coupled to receive at least two address components of said first or second plurality of address components and said first and second start address formation signals during consecutive clock periods, wherein said at least two address components may change every clock period;   said first multiplexor further coupled to a first latch for providing a first component of said at least two address components to said first latch during consecutive clock periods, said first latch having an output coupled to said first combining means and said second combining means, wherein said first component is determined by said first start address formation signal in said first clock period and by said second start address formation signal in said second clock period;   said second multiplexor further coupled to a second latch for providing a second component of said at least two address components to said second latch during consecutive clock periods, said second latch having an output coupled to said first combining means and said second combining means, wherein said second component is determined by said first start address formation signal in said first clock period and by said second start address formation signal in said second clock period;   a third multiplexor coupled to receive said first or second segment base address and said first and second start address formation signals during consecutive clock periods; and   said third multiplexor further coupled to a third latch for providing said first or second segment base address to said third latch during consecutive clock periods based on said first and second start address formation signals, respectively, said third latch having an output coupled to said second combining means.   
     
     
       9. The microprocessor circuit as claimed in claim 8 wherein said first component of said at least two address components is the same as said second component of said at least two address components. 
     
     
       10. A memory management system for a microprocessor having a segmentation unit, wherein said segmentation unit receives a clock signal, said segmentation unit comprising: a three-input adder coupled to a linear address bus, said three-input adder for generating a linear address every clock cycle responsive to a generate address signal;   a two-input adder coupled to an effective address bus, said two-input adder for generating an effective address every clock cycle responsive to said generate address signal;   first and second multiplexors, each coupled to receive a start address formation signal and at least two address components of a set of address components every clock cycle, wherein said start address formation signal and said at least two address components may change every clock cycle;   said first multiplexor further coupled to a first latch for providing a first component of said at least two address components to said first latch wherein said first component is determined by said start address formation signal;   said second multiplexor further coupled to a second latch for providing a second component of said at least two address components to said second latch, wherein said second component is determined by said start address formation signal;   a third multiplexor coupled to receive said start address formation signal and a segment base address every clock cycle, wherein said start address formation signal and said segment base address may change every clock cycle;   said third multiplexor further coupled to a third latch for providing said segment base address to said third latch based on said start address formation signal;   said first latch for holding said first component, said first latch further coupled to said three-input adder and said two-input adder;   said second latch for holding said second component, said second latch further coupled to said three-input adder and said two-input adder; and   said third latch for holding said segment base address, said third latch further coupled to said three-input adder.   
     
     
       11. The segmentation unit of claim 10 further comprising means for checking for segment limit and access rights violations. 
     
     
       12. The segmentation unit as recited in claim 10 wherein said start address formation signal is provided during a first clock cycle for a first memory reference and during a second clock cycle for a second memory reference and said generate address signal is provided during said second clock cycle for said first memory reference and during a third clock cycle for said second memory reference. 
     
     
       13. The segmentation unit as recited in claim 10 wherein said first component is one of a relative base index, an instruction pointer address, and an effective address generated in a previous clock cycle, and said second component is one of said relative base index, said effective address, and a displacement.