Apparatus for processing image motion compensation information for an image processing system

Abstract

An apparatus for processing image motion compensation information for an image processing system, which can add image motion compensation information and assign the bit number suitable for a specific data size required in signal processing added data with a simple structure. The apparatus includes an adding section for adding an inputted difference data per block and a data previously stored in a frame memory, an overflow/underflow checking section for checking overflow/underflow of summed data and reducing the bit size of the added data, and an overflow/underflow executing section for output-controlling the added data according to the checked overflow/underflow.

What is claimed is: 
     
       1. An apparatus for processing image motion compensation information for an image processing system comprising: means for adding an inverse quantized data for motion-compensation and a frame memory data;   means for determining a sign bit of added data;   means for checking overflow/underflow of said added data and reducing the bit size of said added data according to checked overflow/underflow;   overflow/underflow excuting means for output-controlling said added data according to said checked overflow/underflow; and   latch means for providing final data by adding said sign bit to overflow/underflow executed data.   
     
     
       2. An apparatus as claimed in claim 1, wherein said sign bit determining means determines a sign bit SIGN and is composed of a logic, SIGN=IMSB*MMSB+IMSB*A4+MMSB*A4, with respect to each of most significant bits IMSB and MMSB of input data of said adding means and the carry data A4 of said added data. 
     
     
       3. An apparatus as claimed in claim 1, wherein said overflow/underflow executing means comprises: a plurality of OR gates for providing the value of "1" for all input data if overflow is checked; and   a plurality of AND gates for providing the value of "0" for all input data if underflow is checked.   
     
     
       4. An apparatus as claimed in claim 1, further comprising a plurality of D flip-flops as a data latch for synchronizing data processing timing of said adding means, overflow/underflow checking means, overflow/underflow executing means and latch means in accordance with an input clock. 
     
     
       5. An apparatus as claimed in claim 1, wherein said overflow/underflow detecting means comprises a circuit for checking overflow/underflow of said added data;   a circuit for checking overflow/underflow in reducing said bit size; and   an output controlling circuit for decoding each output of said checking circuits and providing a decoded output as an information for controlling output of said overflow/underflow executing means.   
     
     
       6. An apparatus as claimed in claim 5, wherein said overflow/underflow checking circuit of said added data detects overflow OF and underflow UF, respectively, and is composed of a logic, OF=IMSB*MMSB*MSB, UF=IMSB*MMSB*MSB, with respect to each of most significant bits IMSB, MMSB of input data of said adding means and the most significant bit MSB of said added data. 
     
     
       7. An apparatus as claimed in claim 5, wherein said overflow/underflow checking circuit in reducing said bit size detects overflow OF and underflow UF, respectively, and is composed of a logic, OF=SIGN*A3, UF=SIGN*A3, with respect to said sign bit SIGN and the most significant bit A3 of said added data. 
     
     
       8. An apparatus as claimed in claim 5, wherein said output controlling circuit comprises: an OR gate for OR-gating overflows checked by said checking circuits; and   an AND gate for AND gating underflows checked by said checking circuits.