High-resolution synchronous delay line

Abstract

A synchronous delay line (SDL) for generating delayed signals synchronized with a clock signal is described. The present SDL includes a phase generator and a plurality of serially coupled voltage controlled delay elements. The phase generator takes the clock signal and generates a first trigger signal and a second trigger signal, which are substantially deskewed with respect to each other. Each of the delay elements receives two trigger inputs and outputs a delayed signal and two trigger outputs. The first and second trigger signals are coupled to one of the delay elements as trigger inputs. Each transition of the first and second trigger signals triggers the propagation of two waves through the delay line. The present SDL has a minimum tap-to-tap delay of only one inverter delay, versus a minimum tap-to-tap delay of two NAND gates in prior SDLs. Thus, the present SDL provides for double the number of output taps, and hence, double the resolution as compared to prior SDLs.

What is claimed is: 
     
       1. An integrated circuit synchronous delay line for generating delayed signals synchronized with a clock signal, comprising: a) a phase generator coupled to said clock signal generating a first phasing signal approximately 90° out of phase with said clock signal and a second phasing signal substantially in phase with said clock signal, said phase generator generating a first trigger signal WVA 0  and a second trigger signal WVB 0 , said first trigger signal WVA 0  and said second trigger signal WVB 0  being substantially deskewed with respect to each other, said first trigger signal WVA 0  being complementary to said second trigger signal WVB 0 , said first and second trigger signals WVA 0  and WVB 0  being substantially in phase with said clock signal, said phase generator further comprising: i) a master latch receiving said clock signal and outputting said first phasing signal;   ii) a slave latch receiving said first phasing signal and said clock signal and outputting said second phasing signal; and   iii) a first pass network generating said first trigger signal WVA 0  and said second trigger signal WVB 0 , said first pass network being coupled to said clock signal, said first phasing signal and said second phasing signal; and     b) a plurality of serially coupled voltage controlled delay elements, each delay element having two trigger inputs, a delayed signal tap output, two trigger outputs, and a clock input, the plurality of serially coupled voltage controlled delay elements including a multiplicity of even voltage controlled delay elements and odd delay elements, a first of the even voltage controlled delay elements having its trigger inputs coupled to the first trigger signal WVA 0  and the second trigger signal WVB 0 , each of the remaining even delay elements having its trigger inputs coupled to the trigger outputs of an adjacent odd delay element, all of the odd delay elements having their trigger inputs coupled to trigger outputs of an adjacent even delay element, some of the plurality of serially coupled voltage controlled delay elements having their clock inputs coupled to the first phasing signal and others of the plurality of serially coupled voltage controlled delay elements having their clock inputs coupled to the second phasing signal, wherein during a first clock cycle of said clock signal a first transition by the first trigger signal WVA 0  from a low voltage level to a high voltage level triggers transistions of the delayed signal tap outputs of the even voltage controlled delay elements, and a second transition by the second trigger signal WVB 0  from the high voltage to the low voltage triggers transistions of the delayed signal tap outputs of the odd controlled delay elements, and wherein during a second clock cycle following said first clock cycle a third transition by the first trigger signal WVA.sub. 0 from the high voltage level to the low voltage level triggers transitions of the delayed signal tap outputs of the odd voltage controlled delay elements and a fourth transition by the second trigger signal WVB 0  from the low voltage level to the high voltage level triggers transitions of the delayed signal tap outputs of the even voltage controlled delay elements.   
     
     
       2. The integrated circuit synchronous delay line of claim 1 wherein said each of said plurality of voltage controlled delay elements comprises: a) a first inverting means for inverting one of said trigger inputs and outputting one of said trigger outputs;   b) a second inverting means for inverting the other of said trigger inputs and outputting the other of said trigger outputs; and   c) a second pass network coupled to said trigger outputs, said second pass network outputting one of said trigger outputs as said delayed signal tap output.   
     
     
       3. The integrated circuit synchronous delay line of claim 2 wherein said first inverting means and said second inverting means comprise inverters. 
     
     
       4. The integrated circuit synchronous delay line of claim 2 wherein each of said delay elements further comprises a device for controlling a delay between said clock signal and said delayed signal tap output, said device for controlling a duration of said delay being coupled to said trigger outputs, said delay varying in response to a control voltage. 
     
     
       5. The integrated circuit synchronous delay line of claim 4 wherein said device for controlling a delay comprises: a) a first voltage controlled capacitive device having capacitance coupled to one of said trigger outputs, the capacitance of said first voltage controlled capacitive device carrying in response to said control voltage; and   b) a second voltage controlled capacitive device coupled to the other of said trigger outputs, the capacitance of said second voltage controlled capacitive device varying in response to said control voltage.   
     
     
       6. The integrated circuit synchronous delay line of claim 5 further comprising a control signal generator for generating said control voltage. 
     
     
       7. The integrated circuit synchronous delay line of claim 6 wherein said control signal generator comprises a sample and hold circuit. 
     
     
       8. The integrated circuit synchronous delay line of claim 1 wherein said first pass network comprises: a) a first multiplicity of transistors coupled to said clock signal, said second phasing signal and said master latch, said first multiplicity of transistors generating said first trigger signal WVA 0  ; and   b) a second multiplicity of transistors coupled to said clock signal, said first phasing signal and said slave latch, said second multiplicity of transistors generating said second trigger signal WVB 0 .   
     
     
       9. The integrated circuit synchronous delay line of claim 8 wherein said first multiplicity of transistors comprises: a) a first P-type transistor coupled to said second phasing signal, said clock signal and said first trigger signal WVA 0  ;   b) a first N-type transistor coupled to said second phasing signal, said clock signal and said first trigger signal WVA 0  ;   c) a second N-type transistor coupled to said clock signal and said first trigger signal WVA 0  ;   d) a third N-type transistor coupled to said master latch, a first voltage level, and said second N-type transistor;   e) a second P-type transistor coupled to said clock signal and said first trigger signal WVA 0  ; and   f) a third P-type transistor coupled to a second voltage level, said master latch and said second P-type transistor.   
     
     
       10. The integrated circuit synchronous delay line of claim 8 wherein said second multiplicity of transistors comprises: a) a first P-type transistor coupled to said slave latch, said clock signal and said second trigger signal WVB 0  ;   b) a first N-type transistor coupled to said slave latch, said clock signal and said second trigger signal WVB 0  ;   c) a second N-type transistor coupled to said clock signal and said second trigger signal WVB 0  ;   d) a third N-type transistor coupled to said first phasing signal, a first voltage level, and said second N-type transistor;   e) a second P-type transistor coupled to said clock signal and said second trigger signal WVB 0  ; and   f) a third P-type transistor coupled to a second voltage level, said first phasing signal and said second P-type transistor.   
     
     
       11. The integrated circuit synchronous delay line of claim 2 wherein each second pass network within an even voltage controlled delay element during said first clock cycle couples to said delayed signal tap output one of the two trigger outputs that is triggered by the first transition of the first trigger signal WVA 0  from the low voltage level to the high voltage level, and wherein during the second clock cycle the second pass network couples to the delayed signal tap output one of the two trigger outputs that is triggered by the fourth transition of the second trigger signal WVB 0  from the low voltage to the high voltage. 
     
     
       12. The integrated circuit synchronous delay line of claim 11 wherein each second pass network within an odd voltage controlled delay element during the first clock couples to said delayed signal tap output one of said two trigger outputs that is triggered by the second trigger signal from the high voltage level to the low voltage level and wherein during the second clock cycle said second pass network couples to said delayed signal output one of said two trigger outputs that is triggered by the third transition by the first trigger signal WVA 0  from the high voltage level to the low voltage level. 
     
     
       13. The integrated circuit synchronous delay line of claim 12 wherein each second pass networks within an even voltage controlled delay element couples to said delayed signal tap output during the first clock signal one of said two trigger outputs of said even delay element that is triggered by the first transition by the first trigger signal WVA 0  from the low voltage level to the high voltage level and wherein during the second clock cycle the second pass network couples to said delayed signal tap output one of said two trigger outputs of said even delay element that is triggered by the fourth transition of the second trigger signal WVB 0  from the low voltage to the high voltage. 
     
     
       14. The integrated circuit synchronous delay line of claim 13 wherein each of the second pass networks within an odd voltage controlled delay element during said first clock cycle couples to said delayed signal tap output one of said two trigger outputs of said odd delay element that is triggered by the second transition by the second trigger signal from the high voltage level to the low voltage level and wherein during said second clock cycle said second pass network couples to said delayed signal tap output one of said two trigger outputs of said odd delay element that is triggered by the third transition by the first trigger signal WVA 0  from the high voltage level to the low voltage level. 
     
     
       15. An integrated circuit synchronous delay line for generating delayed signals synchronized with a clock signal, comprising: a) a phase generator coupled to said clock signal and generating a first phasing signal approximately 90° out of phase with said clock signal and a second phasing signal substantially in phase with said clock signal, said phase generator generating a first trigger signal WVA 0  and a second trigger signal WVB 0 , said first trigger signal WVA 0  and said trigger signal WVB 0  being substantially deskewed with respect to each other, said first trigger signal WVA 0  being complementary to said second trigger signal WVB 0 , said first and second trigger signals WVA 0  and WVB 0  being substantially in phase with said clock signal, said phase generator further comprising: i) a mater latch receiving said clock signal and outputting said first phasing signal;   ii) a slave latch receiving said first phasing signal and said clock signal and outputting said second phasing signal; and   iii) a first pass network generating said first trigger signal WVA 0  and said second trigger signal WVB 0 , said first pass network being coupled to said clock signal, said first phasing signal and said second phasing signal; and     b) a plurality of serially coupled voltage controlled delay elements, each voltage controlled delay element having two trigger inputs, a delayed signal tap output, two trigger outputs and a clock input, said plurality of serially coupled voltage controlled delay elements including a multiplicity of even voltage controlled delay elements and odd voltage controlled delay elements, a first of the even voltage controlled delay elements having its trigger inputs coupled to the first trigger signal WVA 0  and the second trigger signal WVB 0 , and each of the remaining even delay elements having its trigger inputs coupled to the trigger outputs of an adjacent odd delay element, and all of the odd delay elements having their trigger inputs coupled to trigger outputs of an adjacent even delay element, some of the plurality of serially coupled voltage controlled delay elements having their clock inputs coupled to the first phasing signal and others of the plurality of serially coupled voltage controlled delay elements having their clock inputs coupled to the second phasing signal, wherein during a first clock cycle of said clock signal a first transition by the first trigger signal WVA 0  from a low voltage level to a high voltage level triggers transitions of the delayed signal tap outputs of the even voltage controlled delay elements and a second transition by the second trigger signal WVB 0  from the high voltage to the low voltage triggers transitions of the delayed signal tap outputs of the odd voltage controlled delay elements, and wherein during a second clock cycle following said first clock cycle a third transition by the first trigger signal WVA 0  from the high voltage level to the low voltage level triggers transitions of the delayed signal tap outputs of the odd voltage controlled delay elements and a fourth transition by the second trigger signal WVB 0  from the low voltage level to the high voltage level triggers transitions of the delayed signal tap outputs of the even voltage controlled delay elements.   
     
     
       16. The integrated circuit synchronous delay line of claim 15 wherein said first pass network comprises: a) a first multiplicity of transistors coupled to said clock signal, said second phasing signal and said master latch, said first multiplicity of transistors generating said first trigger signal WVA 0  ; and   b) a second multiplicity of transistors coupled to said clock signal, said first phasing signal and said slave latch, said second multiplicity of transistors generating said second trigger signal WVB 0 .   
     
     
       17. The integrated circuit synchronous delay line of claim 16 wherein the first multiplicity of transistors comprises: a) a first P-type transistor coupled to said second phasing signal, said clock signal and said first trigger signal WVA 0  ;   b) a first N-type transistor coupled to said second phasing signal, said clock signal and said first trigger signal WVA 0  ;   c) a second N-type transistor coupled to said clock signal and said first trigger signal WVA 0  ;   d) a third N-type transistor coupled to said master latch, a first voltage level, and said second N-type transistor;   e) a second P-type transistor coupled to said clock signal and said first trigger signal WVA 0  ; and   f) a third P-type transistor coupled to a second voltage level, said master latch and said second P-type transistor.   
     
     
       18. The integrated circuit synchronous delay line of claim 15 wherein each of said voltage controlled delay elements comprise: a) a first inverting means for inverting one of said trigger inputs and outputting one of said trigger outputs;   b) a second inverting means for inverting the other of said trigger inputs and outputting the other of said trigger outputs; and   c) a second pass network coupled to said trigger outputs, said second pass network outputting one of said trigger outputs as said delayed signal tap output.   
     
     
       19. The integrated circuit synchronous delay line of claim 18 wherein each of said voltage controlled elements further comprise a device for controlling a delay between said clock signal and sad delayed signal tap output, said device being coupled to said trigger outputs, said delay varying in response to a control voltage. 
     
     
       20. The integrated circuit synchronous delay line of claim 19 wherein the device for controlling a delay comprises: a) a first voltage controlled capacitive device having capacitance coupled to one of said trigger outputs, the capacitance of said first voltage controlled capacitive device varying in response to said controlled voltage; and   b) a second voltage controlled capacitive device coupled to the other of said trigger outputs, the capacitance of said second voltage controlled capacitive device varying in response to said control voltage.   
     
     
       21. The integrated circuit synchronous delay line of claim 20 further comprising a control signal generator for generating said control voltage. 
     
     
       22. The integrated circuit synchronous delay line of claim 21 wherein said control signal generator comprises a sample and hold circuit coupled to trigger outputs from one of said delay elements. 
     
     
       23. An integrated circuit synchronous delay line for generating delayed signals synchronized with a clock signal, comprising: a) a phase generator coupled to the clock signal generating a first phasing signal approximately 90° out of phase with said clock signal and a second phasing signal substantially in phase with said clock signal, said phase generator generating a first trigger signal and a second trigger signal, the first trigger signal and the second trigger signal being deskewed with respect to each other, the first trigger signal being complementary to the second trigger signal, said first and second trigger signals WVA 0  and WVB 0  being substantially in phase with said clock signal, phase generator further comprising: i) a master latch receiving the clock signal and outputting the first phasing signal;   ii) a slave latch receiving the first phasing signal and the clock signal and outputting the second phasing signal; and   iii) a first pass network generating the first trigger signal and the second trigger signal, the first pass network being coupled to the clock signal, the first phasing signal and the second phasing signal; and     b) a plurality of serially coupled voltage controlled delay elements, each delay element having two trigger inputs, a delayed signal output, two trigger outputs, and a clock input, the plurality of serially coupled voltage controlled delay elements including a first multiplicity of voltage controlled delay elements and a second multiplicity of voltage controlled delay elements, one of the first multiplicity of voltage controlled delay elements having its trigger inputs coupled to the first trigger signal and the second trigger signal, all other delay elements of the first multiplicity of voltage controlled delay elements having their trigger inputs coupled to the trigger outputs of an adjacent one the second multiplicity of voltage controlled delay elements, all of the second multiplicity of voltage controlled delay elements having their trigger inputs coupled to trigger outputs of an adjacent one of the first multiplicity of voltage controlled delay elements, some of the plurality of serially coupled voltage controlled delay elements having their clock inputs coupled to the first phasing signal and others of the plurality of serially coupled voltage controlled delay elements having their clock inputs coupled to the second phasing signal, wherein during a first clock cycle of the clock signal a first transition by the first trigger signal from a low voltage level to a high voltage level triggers transitions of the delayed signal outputs of the first multiplicity of voltage controlled delay elements, and a second transition by the second trigger signal from the high voltage level to the low voltage level triggers transitions of the delayed signal outputs of the second multiplicity of voltage controlled delay elements, and wherein during a second clock cycle following said first clock cycle a third transition by the first trigger signal from the high voltage level to the low voltage level triggers transitions of the delayed signal outputs of the second multiplicity of voltage controlled delay elements, and a fourth transition by the second trigger signal from the low voltage level to the high voltage level triggers transitions of the delayed signal outputs of the first multiplicity of voltage controlled delay elements.   
     
     
       24. The integrated circuit synchronous delay line of claim 23 wherein each of the plurality of voltage controlled delay elements comprises: a) a first inverting means for inverting one of the trigger inputs and outputting one of the trigger outputs;   b) a second inverting means for inverting the other of the trigger inputs and outputting the other of the trigger outputs; and   c) a first pass network coupled to the trigger outputs, the second pass network outputting one of said trigger outputs as the delayed signal output.   
     
     
       25. The integrated circuit synchronous delay line of claim 23 wherein each of the plurality of voltage controlled delay elements further comprises a device for controlling a duration of a delay between the clock signal and the delayed signal output, the device for controlling a duration of a delay being coupled to the trigger outputs, the duration of the delay varying in response to a control voltage. 
     
     
       26. The integrated circuit synchronous delay line of claim 23 wherein the first pass network comprises: a) a first multiplicity of transistors coupled to the clock signal, the second phasing signal and the master latch, the first multiplicity of transistors generating the first trigger signal; and   b) a second multiplicity of transistors coupled to the clock signal, the first phasing signal and the slave latch, the second multiplicity of transistors generating the second trigger signal.   
     
     
       27. The integrated circuit synchronous delay line of claim 26 wherein the first multiplicity of transistors comprises: a) a first P-type transistor coupled to the second phasing signal, the clock signal and the first trigger signal;   b) a first N-type transistor coupled to the second phasing signal, said clock signal and the first trigger signal;   c) a second N-type transistor coupled to the clock signal and the first trigger signal;   d) a third N-type transistor coupled to the master latch, a first voltage level, and the second N-type transistor;   e) a second P-type transistor coupled to the clock signal and the first trigger signal; and   f) a third P-type transistor coupled to a second voltage level, the master latch and the second P-type transistor.   
     
     
       28. The integrated circuit synchronous delay line of claim 23 wherein the second multiplicity of transistors comprises: a) a first P-type transistor coupled to the slave latch, the clock signal and the second trigger signal;   b) a first N-type transistor coupled to the slave latch, the clock signal and the second trigger signal;   c) a second N-type transistor coupled to the clock signal and the second trigger signal;   d) a third N-type transistor coupled to the first phasing signal, a first voltage level, and the second N-type transistor;   e) a second P-type transistor coupled to the clock signal and said second trigger signal; and   f) a third P-type transistor coupled to a second voltage level, the first phasing signal and the second P-type transistor.