Undervoltage protection circuit, system and method of operating same

Abstract

An undervoltage protection circuit, system and method is prodded for sending a reset signal to an electronic device during undervoltage time periods in which the device power supply voltage is less than a desired amount. The protection circuit includes a sensing circuit and a latching network adapted to quickly discharge a storage capacitor when the sensing circuit senses the undervoltages. A buffer network is included to send a reset signal to the electronic device whenever the storage capacitor discharges to a low latched level. The reset signal exists substantially throughout the undervoltage time period and also for a set delay period after the undervoltage time period ceases. During receipt of the reset signal, the electronic device will be inhibited from incurring damage or loss of data.

What is claimed is: 
     
       1. An undervoltage protection circuit comprising: a sensing circuit capable of receiving a DC power supply voltage and a reference voltage;   a latching network coupled to said sensing circuit, said latching network is adapted to discharge a storage capacitor to a latched voltage value during an undervoltage time period in which said DC power supply voltage is less than said reference voltage; and   a buffer means for receiving said latched voltage value and for producing a reset signal during said undervoltage time period and for a set delay period after said undervoltage time period ceases.   
     
     
       2. The protection circuit as recited in claim 1, wherein said reset signal is a bistable signal which will remain in a fixed logic state for substantially said undervoltage time period. 
     
     
       3. The protection circuit as recited in claim 1, wherein said sensing circuit comprises: a voltage divider network and a diode network connected to said DC power supply voltage;   a comparator having an output, an inverting input and a non-inverting input, said inverting input is connected to said voltage divider network and said non-inverting input is connected to said diode network; and   a transistor having a collector connected to said latching network, an emitter connected to a ground voltage and a base connected to the output of said comparator.   
     
     
       4. The protection circuit as recited in claim 1, wherein said latching network comprises a conductive discharge path capable of being formed between said storage capacitor and a ground voltage. 
     
     
       5. The protection circuit as recited in claim 1, wherein said sensing circuit, said latching network and said buffer means are all powered by said DC power supply voltage. 
     
     
       6. The protection circuit as recited in claim 1, wherein said buffer means comprises: an amplifier having a voltage shifted output controlled by said storage capacitor; and   a signal generator connected to said voltage shifted output for producing said reset signal.   
     
     
       7. The protection circuit as recited in claim 6, wherein said amplifier comprises: first and second transistors, each transistor having a collector, emitter and base, wherein the collector and emitter of the first transistor is connected to the collector and base, respectively, of the second transistor   a pull-up resistor connected to the common connected collectors of the first and second transistors; and   a pull-down resistor connected to the emitter of the second transistor.   
     
     
       8. The protection circuit as recited in claim 6, wherein said signal generator comprises a schmitt trigger. 
     
     
       9. A system for inhibiting the operation of a load device, comprising: a load device coupled to receive power from a DC power supply voltage;   an undervoltage protection circuit powered by said DC power supply voltage and connected to send a reset signal to said load device during an undervoltage time period in which said DC power supply voltage is less than a reference voltage, to continue sending said reset signal for a set delay period after said voltage time period ceases, and to maintain coupling of said DC power supply voltage and to said load device during said undervoltage time period and during said set delay period after said undervoltage time period ceases, said protection circuit comprising: a sensing circuit adapted to compare said DC power supply voltage with said reference voltage and produce a relatively low voltage during said undervoltage time period;   a latching network coupled to receive said low output voltage and programmably form a corresponding conductive discharge path;   a current limiting resistor and storage capacitor coupled to said latching network to provide a discharge of said capacitor through said conductive discharge path; and   a buffer means for receiving voltage from said discharged capacitor and for producing said reset signal.     
     
     
       10. The system as recited in claim 9, wherein said buffer means continues to produce said reset signal for a set delay period after the time in which said DC power supply voltage ceases to be less than said reference voltage. 
     
     
       11. The system as recited in claim 9, wherein said reset signal is a bistable signal which will remain in a fixed logic state for substantially said undervoltage time period. 
     
     
       12. The system as recited in claim 9, wherein said latching network comprises a programmable unijunction transistor having a gate, an anode and a cathode, said gate is connected to receive said relatively low voltage from the sensing circuit and produce corresponding said conductive discharge path from said anode to said cathode. 
     
     
       13. The system as recited in claim 12, wherein said gate is connected to a manual switch, said switch is adapted to manually couple said gate to a ground voltage. 
     
     
       14. The system as recited in claim 12, wherein said anode is connected to one end of said current limiting resistor, the other end of said current limiting resistor is connected to said DC power supply voltage, said current limiting resistor is appropriately sized to modulate the amount of current sent through said discharge path. 
     
     
       15. The system as recited in claim 9, wherein said buffer means comprises: an amplifier which includes: first and second transistors, each transistor having a collector, emitter and base, wherein the collector and emitter of the first transistor is connected to the collector and base, respectively, of the second transistor;   a pull-up resistor connected to the common connected collectors of the first and second transistors;   a pull-down resistor connected to the emitter of the second transistor; and     a signal generator connected to the emitter of the second transistor.   
     
     
       16. A method for inhibiting the operation of a load device, comprising: providing a DC power supply connected to a load device;   providing a protection circuit which includes a charged capacitor and a buffer network coupled to said charged capacitor;   sensing a voltage from said DC power supply which is less than a reference voltage;   discharging said capacitor to a latched voltage value; and   level shifting said latched voltage value through said buffer network to produce a reset output signal for inhibiting said load device during times in which said DC power supply is less than a reference voltage and for inhibiting said load device for a set delay period after said DC power supply becomes greater than said reference voltage; and   maintaining connection of said DC power supply to said load device during times in which said load device is inhibited.   
     
     
       17. The method as recited in claim 16, wherein said sensing step comprises: comparing said DC power supply voltage with said reference voltage; and   outputting a relatively low voltage to a latching circuit connected to said charged capacitor whenever said DC power supply voltage is less than said reference voltage.   
     
     
       18. The method as recited in claim 16, wherein said discharging step comprises programmably forming a discharge path between said charged capacitor and a ground voltage. 
     
     
       19. The method as recited in claim 16, wherein said level shifting step comprises adjusting the magnitude of said reset signal to accommodate various logic magnitudes. 
     
     
       20. The method as recited in claim 16, further comprising continuing to produce said reset output for a set delay period after the time in which said DC power supply voltage ceases to be less than said reference voltage.