Method and apparatus for qualifying data peaks

Abstract

A system and method for qualifying data peaks. A post-peak eliminator receives digital signals representing the amplitude of signal peaks. The digital value of a received peak is stored and compared with the value of subsequently received peaks. The peak having the largest amplitude is assumed to be the valid peak. The post-peak eliminator eliminates all invalid post-peaks and applies a signal stream representing valid peaks and any invalid pre-peaks to a pre-peak eliminator. The pre-peak eliminator includes a shift register and a control circuit therefor that operates on a state machine basis. The shift register receives and stores all signals, but eliminates any invalid pre-peaks immediately upon a determination that a received signal represents an invalid peak.

We claim: 
     
       1. A system for eliminating invalid peaks from a received signal stream containing valid data peaks, said system comprising: means for receiving said signal stream with each of said peaks being represented as a binary number whose magnitude specifies the amplitude of the peak represented by said binary number;   a post peak eliminator for eliminating invalid post peaks received subsequent to a valid data peak in said signal stream with each of said invalid post peaks being of a lesser amplitude than said valid data peak and being of the same polarity as said valid data peak, said post peak eliminator comprising;   digital hold register means for storing a digital value representing the amplitude of a received peak,   means for comparing a digital value representing the amplitude of each subsequently received peak with the digital value of a previously received peak currently stored in said hold register means,   means for outputting a data pulse representing a subsequently received peak if the digital value of said subsequently received peak is greater than the digital value of the peak currently stored in said hold register means and for updating said hold register means with the digital value of said subsequently received peak,   means for maintaining the digital value for a peak currently in said hold register means while inhibiting the outputting of a data pulse in response the reception of a subsequent peak of a lessor digital value than the digital value of the peak currently in said hold register means; and   means for outputting a clock pulse and a polarity signal concurrent with the outputting of each data pulse with said polarity signal specifying the polarity of the peak represented by each outputted data pulse;   said system further including a pre-peak eliminator for receiving each data pulse and clock pulse and said polarity signals outputted by said post peak eliminator;   means in said pre-peak eliminator operable in response to said reception of said outputted data pulses and said clock pulses and said polarity signals to eliminate the received data pulses representing invalid pre-peaks and for applying a data pulse representing each valid peak to a utilization means.   
     
     
       2. The system of claim 1 wherein said post peak detector further includes threshold means for inhibiting the outputting of data pulses representing received peaks having less than a fixed amplitude. 
     
     
       3. The system of claim 1 wherein said post peak detector further includes dynamically controlled threshold means for inhibiting the outputting of data pulses representing peaks having less than a variably specified amplitude; said dynamically controlled threshold means comprising means controlled by the digital value of a received negative peak for specifying the threshold to be used for the reception of signals representing received positive peaks; and   said dynamically controlled threshold means further comprising means controlled by the digital value of a received positive peak for specifying the threshold to be used for the reception of signals representing received negative peaks.   
     
     
       4. The system of claim 1 wherein said post peak detector further includes dynamically controlled threshold means for inhibiting the outputting of data pulses representing received peaks having less than a variably specified amplitude; said dynamically controlled threshold means comprising:   memory means for receiving as address information the digital value representing the amplitude of each received peak;   said memory means being responsive to each receipt of a digital value for outputting from said memory means a threshold value representing said digital value;   means for applying said threshold value from said memory means to threshold register means;   said memory means and said threshold register means being controlled by the digital value of a negative peak for specifying the threshold to be used for the reception of signals representing positive peaks; and   said memory means and said threshold register means being controlled by the digital value of a positive peak for specifying the threshold to be used for the reception of signals representing negative peaks.   
     
     
       5. The system of claim 4 wherein said threshold register means comprises: a positive threshold register for receiving from said memory the threshold to be used for the reception of signals representing positive peaks; and   a negative threshold register for receiving from said memory the threshold to be used for the reception of signals representing negative peaks.   
     
     
       6. The system of claim 5 wherein said system further comprises: means responsive to the reception of a signal whose amplitude exceeds a negative threshold specified by said negative threshold register for entering into said positive threshold register a positive threshold value outputted from said memory means; and   means responsive to the reception of a signal whose amplitude exceeds a positive threshold specified by said positive threshold register for entering into said negative threshold register a negative threshold value outputted from said memory means.   
     
     
       7. The system of claim 1 wherein said hold register means comprises: a positive hold register,   a negative hold register,   means for entering for entering the digital value of a received peak into said positive hold register when said newly received peak has an amplitude greater than the amplitude of a previously received peak whose digital value is currently stored in said positive hold register,   means for entering for entering the digital value of a received peak into said negative hold register when said newly received peak has a negative amplitude greater than the negative amplitude of a previously received peak whose digital value is currently stored in said negative hold register,   means responsive to the entry into said positive hold register of a digital value of a newly received peak for resetting said negative hold register to a baseline value for use on a comparison upon the next receipt of a peak having digital value representing a negative amplitude,   means responsive to the entry into said negative hold register of a digital value of a newly received peak for resetting said positive hold register to a baseline value for use on a comparison upon the next receipt of a peak having a digital value representing a positive amplitude.   
     
     
       8. The system of claim 1 wherein said means for outputting comprises: a peak magnitude comparator for comparing the digital value of a newly received peak with the digital value for a previously received peak stored in said hold register means;   said peak magnitude comparator being effective when the digital value of a newly received peak exceeds the digital value for a previously received peak stored in said hold register means for controlling the generation of a data pulse representing said newly received peak; and   said peak magnitude comparator being effective when the digital value of a newly received peak does not exceed the digital value for a previously received peak stored in said hold register means for inhibiting the generation of a data pulse representing said newly received peak.   
     
     
       9. The system of claim 8 wherein said post peak detector further includes: threshold detector magnitude detector means effective in response to each receipt of a peak whose digital does not exceed a specified threshold for inhibiting the generation of an output pulse to said pre-peak detector;   said threshold detector magnitude detector means being effective in response to each receipt of a peak whose digital does exceed a specified threshold for inhibiting the generation of an output pulse to said pre-peak detector.   
     
     
       10. A system for eliminating invalid peaks from a received signal stream containing valid data peaks, said system comprising: means for receiving said signal stream with each of said peaks being represented as a binary number whose magnitude specifies the amplitude of the peak represented by said binary number;   a post peak eliminator for eliminating invalid post peaks subsequent to a valid data peak in said stream and of a lesser amplitude than said valid data peak, said post peak eliminator comprising;   means in said post peak eliminator for outputting to a pre-peak eliminator data pulses representing valid data peaks as well as invalid pre-peaks preceding a valid data peak and of the same polarity a valid data peak;   means for outputting a clock pulse and a polarity signal concurrent with the outputting of each data pulse with said polarity signal specifying the polarity of the peak represented by each outputted data pulse;   said system further including a pre-peak eliminator for eliminating as invalid pre-peaks preceding a subsequently received valid data peak; said pre-peak eliminator comprising;   a shift register;   means for receiving each data pulse and clock pulse and polarity signal outputted by said post peak eliminator;   means controlled by said received clock pulses for entering into said shift register each received data pulse;   means for advancing said data pulse within said shift register under control of said received clock pulses,   control logic for operating said shift register in response to the reception of said clock pulses and said polarity signals to eliminate from said shift register a data pulse representing an invalid pre-peak if the next received data pulse is of the same polarity as the eliminated data pulse; and   means for outputting as a valid data pulse the last data pulse received in a sequence of received data pulses representing received peaks of the same polarity as specified by said polarity signal.   
     
     
       11. The system of claim 10 wherein said control logic comprises; a data blocker serially interconnecting the output of each shift register stage with the input of the next shift register stage;   means for controlling said data blocker in response to each reception of a clock pulse to determine the shift register stages whose inputs are to be inhibited from receiving a data pulse from the immediate preceding shift register stage.   
     
     
       12. The system of claim 11 wherein said means for controlling said data blocker comprises a state machine operable in response to each reception of a signal pattern represented by the instantaneous value of said polarity signal and the presence or absence of a data pulse when a clock pulse is received for operating said data blocker for controlling the interconnection of a shift register stage with the next adjacent shift register stage. 
     
     
       13. The system of claim 12 comprising means in said data blocker for eliminating invalid pre-peaks that are separated from a subsequently received valid data peak of the same polarity by a bit cell spacing that is limited only by the number of stages in said shift register. 
     
     
       14. A system for eliminating invalid signal peaks from a signal stream containing both invalid signal peaks and valid data signal peaks, said invalid signal peaks comprising invalid pre-peak signals preceding a valid data signal peak as well as invalid post peaks following a valid data signal peak, said system comprising: a post peak eliminator comprising;   means for receiving said signal stream with each of said peaks being represented as a binary number whose magnitude specifies the amplitude of the peak represented by said binary number;   digital processing circuitry responsive to the receipt of peaks in said signal stream for detecting invalid post-peaks and for outputting data pulses representing valid data peaks as well as invalid pre-peaks to a pre-peak eliminator;   said pre-peak eliminator comprising;   a shift register for receiving said pulses outputted from said post peak eliminator; and   control logic for operating said shift register to eliminate an invalid pre-peak in response to the reception of the next received data pulse of the same polarity as the invalid pre-peak pulse.   
     
     
       15. A method of eliminating invalid peaks from a received signal stream containing valid data peaks, said method comprising the steps of: receiving said signal stream with each of said peaks being represented as a binary number whose magnitude specifies the amplitude of the peak represented by said binary number;   operating a post peak eliminator for eliminating invalid post peaks received subsequent to a valid data peak in said signal stream with each of said invalid post peaks being of a lesser amplitude than said valid data peak and being of the same polarity as said valid data peak, method of operating said post peak eliminator comprising the steps of;   storing a digital value representing the amplitude of a received peak in digital hold register means,   comparing a digital value representing the amplitude of each subsequently received peak with the digital value of a previously received peak currently stored in said hold register means,   outputting a data pulse representing a subsequently received peak if the digital value of said subsequently received peak is greater than the digital value of the peak currently stored in said hold register means and for updating said hold register means with the digital value of said subsequently received peak,   maintaining the digital value for a peak currently in said hold register means while inhibiting the outputting of a data pulse in response the reception of a subsequent peak of a lessor digital value than the digital value of the peak currently in said hold register means; and   outputting a clock pulse and a polarity signal concurrent with the outputting of each data pulse with said polarity signal specifying the polarity of the peak represented by each outputted data pulse;   said system further including a pre-peak eliminator for receiving each data pulse and clock pulse and said polarity signals outputted by said post peak eliminator;   said method further comprising the step of:   operating said pre-peak eliminator in response to said reception of said outputted data pulses and said clock pulses and said polarity signals to eliminate the received data pulses representing invalid pre-peaks and for applying a data pulse representing each valid peak to a utilization means.   
     
     
       16. The method of claim 15 wherein said post peak detector further includes threshold means for inhibiting the outputting of data pulses representing received peaks having less than a fixed amplitude. 
     
     
       17. The method of claim 15 wherein said post peak detector further includes dynamically controlled threshold means for inhibiting the outputting of data pulses representing peaks having less than a variably specified amplitude; said method further comprising the step of;   operating said dynamically controlled threshold means including means controlled by the digital value of a received negative peak for specifying the threshold to be used for the reception of signals representing received positive peaks; and   operating said dynamically controlled threshold means including means controlled by the digital value of a received positive peak for specifying the threshold to be used for the reception of signals representing received negative peaks.   
     
     
       18. The method of claim 15 wherein said post peak detector further includes dynamically controlled threshold means for inhibiting the outputting of data pulses representing received peaks having less than a variably specified amplitude; said method further comprising the steps of:   operating said dynamically controlled threshold means comprising:   memory means for receiving as address information the digital value representing the amplitude of each received peak;   operating said memory means being responsive to each receipt of a digital value for outputting from said memory means a threshold value representing said digital value;   operating means for applying said threshold value from said memory means to threshold register means;   operating said memory means and said threshold register means being controlled by the digital value of a negative peak for specifying the threshold to be used for the reception of signals representing positive peaks; and   operating said memory means and said threshold register means being controlled by the digital value of a positive peak for specifying the threshold to be used for the reception of signals representing negative peaks.   
     
     
       19. The method of claim 18 wherein said threshold register means comprises: a positive threshold register for receiving from said memory the threshold to be used for the reception of signals representing positive peaks; and   a negative threshold register for receiving from said memory the threshold to be used for the reception of signals representing negative peaks.   
     
     
       20. The method of claim 19 wherein said method further comprises the steps of: operating means responsive to the reception of a signal whose amplitude exceeds a negative threshold specified by said negative threshold register for entering into said positive threshold register a positive threshold value outputted from said memory means; and   operating means responsive to the reception of a signal whose amplitude exceeds a positive threshold specified by said positive threshold register for entering into said negative threshold register a negative threshold value outputted from said memory means.   
     
     
       21. The method of claim 15 wherein said hold register means comprises: a positive hold register,   a negative hold register,   means for entering for entering the digital value of a received peak into said positive hold register when said newly received peak has an amplitude greater than the amplitude of a previously received peak whose digital value is currently stored in said positive hold register,   means for entering for entering the digital value of a received peak into said negative hold register when said newly received peak has a negative amplitude greater than the negative amplitude of a previously received peak whose digital value is currently stored in said negative hold register,   means responsive to the entry into said positive hold register of a digital value of a newly received peak for resetting said negative hold register to a baseline value for use on a comparison upon the next receipt of a peak having digital value representing a negative amplitude,   means responsive to the entry into said negative hold register of a digital value of a newly received peak for resetting said positive hold register to a baseline value for use on a comparison upon the next receipt of a peak having a digital value representing a positive amplitude.   
     
     
       22. The method of claim 15 wherein said step of outputting a data pulse comprises the step of: operating a peak magnitude comparator for comparing the digital value of a newly received peak with the digital value for a previously received peak stored in said hold register means;   said peak magnitude comparator being effective when the digital value of a newly received peak exceeds the digital value for a previously received peak stored in said hold register means for controlling the generation of a data pulse representing said newly received peak; and   said peak magnitude comparator being effective when the digital value of a newly received peak does not exceed the digital value for a previously received peak stored in said hold register means for inhibiting the generation of a data pulse representing said newly received peak.   
     
     
       23. The method of claim 18 wherein the step of operating said post peak detector further includes: operating threshold detector magnitude detector means effective in response to each receipt of a peak whose digital does not exceed a specified threshold for inhibiting the generation of an output pulse to said pre-peak detector;   said threshold detector magnitude detector means being effective in response to each receipt of a peak whose digital does exceed a specified threshold for inhibiting the generation of an output pulse to said pre-peak detector.   
     
     
       24. A method for eliminating invalid peaks from a received signal stream containing valid data peaks, said method comprising the steps of: receiving said signal stream with each of said peaks being represented as a binary number whose magnitude specifies the amplitude of the peak represented by said binary number;   operating a post peak eliminator for eliminating invalid post peaks subsequent to a valid data peak in said stream and of a lesser amplitude than said valid data peak, said post peak eliminator comprising;   operating means in said post peak eliminator for outputting to a pre-peak eliminator data pulses representing valid data peaks as well as invalid pre-peaks preceding a valid data peak and of the same polarity a valid data peak;   outputting a clock pulse and a polarity signal concurrent with the outputting of each data pulse with said polarity signal specifying the polarity of the peak represented by each outputted data pulse;   said system further including a pre-peak eliminator for eliminating as invalid pre-peaks preceding a subsequently received valid data peak; said pre-peak eliminator comprising;   a shift register;   said method further comprising the steps of:   receiving each data pulse and clock pulse and polarity signal outputted by said post peak eliminator;   by said received clock pulses for entering into said shift register each received data pulse under control of;   advancing said data pulse within said shift register under control of said received clock pulses,   operating said shift register in response to the reception of said clock pulses and said polarity signals to eliminate from said shift register a data pulse representing an invalid pre-peak if the next received data pulse of the same polarity as the eliminated data pulse; and   outputting as a valid data pulse the last data pulse received in a sequence of received data pulses representing received peaks of the same polarity as specified by said polarity signal.   
     
     
       25. The method of claim 24 wherein said controller comprises; a data blocker serially interconnecting the output of each shift register stage with the input of the next shift register stage;   said method further comprising the step of:   controlling said data blocker in response to each reception of a clock pulse to determine the shift register stages whose inputs are to be inhibited from receiving a data pulse from the immediate preceding shift register stage.   
     
     
       26. The method of claim 24 wherein said means for controlling said data blocker comprises a state machine operable in response to each reception of a signal pattern represented by the instantaneous value of said polarity signal and the presence of absence of a data pulse when a clock pulse is received for operating said data blocker for controlling the interconnection of a shift register stage with the next adjacent shift register stage. 
     
     
       27. The method of claim 26 comprising the steps of operating said data blocker for eliminating invalid pre-peaks that are separated from a subsequently received valid data peak of the same polarity by a bit cell spacing that is limited only by the number of stages in said shift register. 
     
     
       28. A method for eliminating invalid signal peaks from a signal stream containing both invalid signal peaks and valid data signal peaks, said invalid signal peaks comprising invalid pre-peak signals preceding a valid data signal peak as well as invalid post peaks following a valid data signal peak, said method comprising the steps of: operating a post peak eliminator for receiving said signal stream with each of said peaks being represented as a binary number whose magnitude specifies the amplitude of the peak represented by said binary number;   operating digital processing circuitry in said post peak eliminator in response to the receipt of peaks in said signal stream for detecting invalid post-peaks and for outputting data pulses representing valid data peaks as well as invalid pre-peaks to a pre-peak eliminator;   operating a pre-peak eliminator including a shift register for receiving said pulses outputted from said post peak eliminator; and   operating said shift register to eliminate an invalid pre-peak in response to the reception of the next received data pulse of the same polarity as the invalid pre-peak pulse.