Field effect transistor having a GaInAs/GaAs quantum well structure

Abstract

A field effect transistor (FET) has a gate electrode, a source electrode and a drain electrode formed on a GaInAs/GaAs quantum well layer structure having an undoped GaAs layer, an impurity doped GaInAs layer, and an undoped GaAs cap layer. The FET further has low resistivity regions formed by ion-implantation in a source region and the drain region of the GaInAs/GaAs quantum well layer structure, and has the impurity doped GaInAs layer as a channel, and further has an undoped GaAs cap layer with a 30-50 nm thickness. An annealing temperature for activating the low resistivity region is not higher than a temperature at which the GaInAs/GaAs quantum well structure substantially breaks and not lower than a temperature at which the sheet resistivity of the low resistivity region sufficiently reduces. The FET thus manufactured has desired characteristics for the GaInAs/GaAs quantum well structure and the low resistivity region, and attains low noise and high speed operation.

I claim: 
     
       1. A field effect transistor comprising; a GaInAs/GaAs quantum well structure having an undoped GaAs buffer layer, an impurity doped GaInAs channel layer and an undoped GaAs cap layer formed on a semi-insulative semiconductor substrate;   a source region and a drain region of a low resistivity formed by ion-implanting impurities from the surface of said GaInAs/GaAs quantum well structure to reach at least said impurity doped GaInAs channel layer and annealing them;   a gate electrode formed on said undoped GaAs cap layer between said source region and the drain region; and   a source electrode and a drain electrode respectively having at least portions thereof formed on said undoped GaAs cap layer and on said source region and said drain region   said undoped GaAs cap layer having a flat surface in an area including at least the area of said gate electrode, said source region and said drain region and having a thickness of 30-50 nm.   
     
     
       2. A field effect transistor according to claim 1, wherein the impurity doped in said impurity doped GaInAs channel layer is an n-type impurity. 
     
     
       3. A field effect transistor according to claim 2 wherein said n-type impurity is silicon. 
     
     
       4. A field effect transistor according to claim 3 wherein said undoped GaAs buffer layer exhibits a p-type semiconductor characteristic, and said undoped GaAs cap layer exhibits an n-type semiconductor characteristic. 
     
     
       5. A field effect transistor according to claim 4, wherein said semi-insulating semiconductor substrate is a semi-insulating GaAs substrate.